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Noise Canceler Enable Register (PnNCE) (n = 4, 6, C, and G)
8.1.6
NCE enables or disables the noise cancel circuit at port n pins in bit units.
Bit
Bit Name
7
Pn7NCE
6
Pn6NCE
5
Pn5NCE
4
Pn4NCE
3
Pn3NCE
2
Pn2NCE
1
Pn1NCE
0
Pn0NCE
Noise Canceler Decision Control Register (PnNCMC) (n = 4, 6, C, and G)
8.1.7
NCMC controls whether 1 or 0 is expected for the input signal to port n pins in bit units.
Bit
Bit Name
7
Pn7NCMC
6
Pn6NCMC
5
Pn5NCMC
4
Pn4NCMC
3
Pn3NCMC
2
Pn2NCMC
1
Pn1NCMC
0
Pn0NCMC
Initial Value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Initial Value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Description
Noise cancel circuit is enabled when a bit in this
register is set to 1, and the pin setting state is
fetched in P4DR, P6DR, or PnPIN in the sampling
cycle set by the PnNCCS.
Description
1 expected: 1 is stored in the port data register
when 1 is input stably.
0 expected: 0 is stored in the port data register
when 0 is input stably.
Rev. 1.00 May 09, 2008 Page 161 of 954
Section 8 I/O Ports
REJ09B0462-0100
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