Irq Enable Register (Ienr) - Renesas Hitachi H8S/2194 Series Hardware Manual

6.2.3

IRQ Enable Register (IENR)

7
Bit :
—
Initial value :
0
—
R/W :
IENR is an 8-bit readable/writable register that controls enabling and disabling of interrupt
requests IRQ5 to IRQ0.
IENR is initialized to H'00 by a reset.
Bits 7 and 6: Reserved
Do not write 1 to them.
Bits 5 to 0: IRQ5 to IRQ0 Enable (IRQ5E to IRQ0E)
These bits select whether IRQ5 to IRQ0 are enabled or disabled.
Bit n
IRQnE Description
0 IRQn interrupt disabled
1 IRQn interrupt enabled
Rev. 2.0, 11/00, page 102 of 1037
6 5 4
— IRQ5E IRQ4E
0 0 0
R/W R/W
—
3 2
IRQ3E IRQ2E IRQ1E
0 0
R/W R/W
1 0
IRQ0E
0 0
R/W R/W
(Initial value)
(n = 5 to 0)