Output Data Register (Pnodr) (N = A To D And F To J); Noise Canceler Enable Register (Pnnce) (N = 6, C, And G) - Renesas H8S/2100 Series Hardware Manual

Output Data Register (PnODR) (n = A to D and F to J)

7.1.5
ODR is a register that stores output data for ports. The upper two bits in PHODR are reserved.
Bit Bit Name
7 Pn7ODR
6 Pn6ODR
5 Pn5ODR
4 Pn4ODR
3 Pn3ODR
2 Pn2ODR
1 Pn1ODR
0 Pn0ODR

Noise Canceler Enable Register (PnNCE) (n = 6, C, and G)

7.1.6
NCE enables or disables the noise cancel circuit at port n pins in bit units.
Bit Bit Name
7 Pn7NCE
6 Pn6NCE
5 Pn5NCE
4 Pn4NCE
3 Pn3NCE
2 Pn2NCE
1 Pn1NCE
0 Pn0NCE
Initial Value R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Initial Value R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Description
ODR stores the output data for the pins that are
used as the general output port.
Description
Noise cancel circuit is enabled when a bit in this
register is set to 1, and the pin setting state is
fetched in P6DR or PnPIN in the sampling cycle
set by the PnNCCS.
Rev. 1.00 Apr. 28, 2008 Page 149 of 994
Section 7 I/O Ports
REJ09B0452-0100