Serial Extended Mode Register (Semr); Noise Filter Setting Register (Snfr) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
15.2.10

Serial Extended Mode Register (SEMR)

b7 b6
— —
0 0
Value after reset:
Bit Symbol Bit Name
b3 to b0 — Reserved
b4 ABCS Asynchronous Mode
Base Clock Select
b5 NFEN Digital Noise Filter
Function Enable
b7, b6 — Reserved
Note 1. Writable only when TE in SCR = 0 and RE in SCR = 0 (both serial transmission and reception are disabled).
NFEN Bit (Digital Noise Filter Function Enable)
This bit enables or disables the digital noise filter function.
When the function is enabled, noise cancellation is applied to the RXDn input signal in asynchronous mode.
In any mode other than above, set the NFEN bit to 0 to disable the digital noise filter function.
When the function is disabled, input signals are transferred as is, as internal signals.
15.2.11

Noise Filter Setting Register (SNFR)

b7 b6
— —
Value after reset: 0 0
Bit Symbol
b2 to b0 NFCS[2:0]
b7 to b3 —
Note 1. Writing to these bits is only possible when the RE and TE bits in the SCR are 0. (both serial transmission and reception are
disabled.)
NFCS[2:0] Bits (Noise Filter Clock Select)
These bits select the sampling clock for the digital noise filter. To use the noise filter in asynchronous mode, set these bits
to 000b.
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
b5 b4 b3 b2
NFEN ABCS — —
0 0 0 0
Description
These bits are read as 0. The write value should be 0.
(Valid only in asynchronous mode)
0: Selects 16 base clock cycles for 1-bit period
1: Selects 8 base clock cycles for 1-bit period
(In asynchronous mode)
0: Noise cancellation function for the RXDn input signal is disabled.
1: Noise cancellation function for the RXDn input signal is enabled.
The NFEN bit should be 0 in any mode other than above.
These bits are read as 0. The write value should be 0.
b5 b4 b3 b2
— — —
0 0 0 0
Bit Name Description
Noise Filter Clock Select In asynchronous mode, the standard setting for the base clock is as
follows.
b2
0 0 0: The clock signal divided by 1 is used with the noise filter.
Other values: Do not make settings other than those listed above.
Reserved These bits are read as 0. The write value should be 0.
b1 b0
— —
0 0
b1 b0
NFCS[2:0]
0 0
b0
15. Serial Communications Interface
R/W
R
1
R/W*
1
R/W*
R
R/W
1
R/W*
R
15-21