Irq Enable Register (Ier); Irq Sense Control Registers H And L (Iscrh, Iscrl) - Renesas H8S Series Hardware Manual

5.3.2

IRQ Enable Register (IER)

IER is an 8-bit readable/writable register that controls the enabling and disabling of interrupt
requests IRQ0 to IRQ5.
Bit Bit Name
−
7, 6
5 IRQ5E
4 IRQ4E
3 IRQ3E
2 IRQ2E
1 IRQ1E
0 IRQ0E
5.3.3

IRQ Sense Control Registers H and L (ISCRH, ISCRL)

The ISCR registers are 16-bit readable/writable registers that select the source that generates an
interrupt request at pins IRQ0 to IRQ5.
Initial Value R/W
All 0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Description
Reserved
Only 0 should be written to these bits.
IRQ5 Enable
The IRQ5 interrupt request is enabled when this bit
is 1.
IRQ4 Enable
The IRQ4 interrupt request is enabled when this bit
is 1.
IRQ3 Enable
The IRQ3 interrupt request is enabled when this bit
is 1.
IRQ2 Enable
The IRQ2 interrupt request is enabled when this bit
is 1.
IRQ1 Enable
The IRQ1 interrupt request is enabled when this bit
is 1.
IRQ0 Enable
The IRQ0 interrupt request is enabled when this bit
is 1.
Rev. 6.00 Mar 15, 2006 page 71 of 570
Section 5 Interrupt Controller
REJ09B0211-0600