Irq Enable Register (Ier) - Renesas H8S Series Hardware Manual

Table 5-3 Correspondence between Interrupt Sources and IPR Settings
Register
IPRA
IPRB
IPRC
IPRD
IPRE
IPRF
IPRG
IPRH
IPRI
IPRJ
IPRK
Note: * Reserved bits. These bits cannot be modified and are always read as 1.
As shown in table 5-3, multiple interrupts are assigned to one IPR. Setting a value in the range from H'0 to H'7 in the 3-bit
groups of bits 6 to 4 and 2 to 0 sets the priority of the corresponding interrupt. The lowest priority level, level 0, is
assigned by setting H'0, and the highest priority level, level 7, by setting H'7.
When interrupt requests are generated, the highest-priority interrupt according to the priority levels set in the IPR registers
is selected. This interrupt level is then compared with the interrupt mask level set by the interrupt mask bits (I2 to I0) in
the extend register (EXR) in the CPU, and if the priority level of the interrupt is higher than the set mask level, an interrupt
request is issued to the CPU.
5.2.3

IRQ Enable Register (IER)

Bit : 7
IRQ7E
Initial value : 0
R/W : R/W
IER is an 8-bit readable/writable register that controls enabling and disabling of interrupt requests IRQ7 to IRQ0.
IER is initialized to H'00 by a reset and in hardware standby mode.
Bits 7 to 0—IRQ7 to IRQ0 Enable (IRQ7E to IRQ0E): These bits select whether IRQ7 to IRQ0 are enabled or
disabled.
Bit n
IRQnE
0
1
6 to 4
IRQ0
IRQ2
IRQ3
IRQ6
IRQ7
Watchdog timer
—*
TPU channel 0
TPU channel 2
TPU channel 4
8-bit timer channel 0
DMAC
SCI channel 1
6 5
IRQ6E IRQ5E
0 0
R/W R/W
Description
IRQn interrupts disabled
IRQn interrupts enabled
4 3 2
IRQ4E IRQ3E IRQ2E
0 0 0
R/W R/W R/W
Bits
2 to 0
IRQ1
IRQ4
IRQ5
DTC
Refresh timer
A/D converter
TPU channel 1
TPU channel 3
TPU channel 5
8-bit timer channel 1
SCI channel 0
SCI channel 2
1 0
IRQ1E IRQ0E
0 0
R/W R/W
Rev.6.00 Oct.28.2004 page 85 of 1016
(Initial value)
(n = 7 to 0)
REJ09B0138-0600H