Noise Canceller - Renesas R8C Series User Manual

R8C/1A Group, R8C/1B Group
16.3.5

Noise Canceller

The states of pins SCL and SDA are routed through the noise canceller before being latched internally.
Figure 16.44 shows a Block Diagram of Noise Canceller.
The noise canceller consists of two cascaded latch and match detector circuits. When the SCL pin input signal
(or SDA pin input signal) is sampled on f1 and two latch outputs match, the level is passed forward to the next
circuit. When they do not match, the former value is retained.
SCL or SDA
input signal
f1 (sampling clock)
Figure 16.44 Block Diagram of Noise Canceller
Rev.1.30 Dec 08, 2006
REJ09B0252-0130
f1 (sampling clock)
C
D Q
Latch
Period of f1
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16. Clock Synchronous Serial Interface
C
Match
D Q
detection
Latch
circuit
Internal SCL
or SDA signal