Serial Timer Control Register (Stcr) - Renesas H8S/2100 Series Hardware Manual

3.2.3

Serial Timer Control Register (STCR)

STCR enables or disables register access, IIC operating mode, and on-chip flash memory, and
selects the input clock of the timer counter.
Initial
Bit Bit Name Value
7 IICX2 0

6 0
5 IICX0 0
4 IICE 0
R/W Description
2
R/W I C_2 Transfer Rate Select
These bits control the IIC_2 operation. These bits
select the transfer rate in master mode together with
bits CKS2 to CKS0 in the I
(ICMR_2). For details on the transfer rate, see table
17.4.
R/W Reserved
The initial value should not be changed.
2
I C_0 Transfer Rate Select
These bits control the IIC_0 operation. These bits
select the transfer rate in master mode together with
bits CKS2 to CKS0 in the I
(ICMR_0). For details on the transfer rate, see table
17.4.
2
R/W I C Master Enable
When the RELOCATE bit is cleared to 0, enables or
disables CPU access for IIC registers (ICCR, ICSR,
ICDR/SARX, ICMR/SAR, and ICRES), PWMX registers
(DADRAH/DACR, DADRAL, DADRBH/DACNTH, and
DADRBL/DACNTL), and SCI registers (SMR, BRR, and
SCMR).
0: SCI_1 registers are accessed in areas from
H'(FF)FF88 to H'(FF)FF89 and from H'(FF)FF8E to
H'(FF)FF8F.
Access is prohibited in areas from H'(FF)FFD8 to
H'(FF)FFD9 and from H'(FF)FFDE to H'(FF)FFDF.
1: Access is prohibited in areas from H'(FF)FF88 to
H'(FF)FF89 and from H'(FF)FF8E to H'(FF)FF8F.
IIC_0 registers are accessed in areas from
H'(FF)FFD8 to H'(FF)FFD9 and from H'(FF)FFDE to
H'(FF)FFDF.
ICRES is accessed in areas of H'(FF)FEE6.
When the RELOCATE bit is set to 1, this bit is disabled.
For details, see section 3.2.4, System Control Register
3 (SYSCR3) and section 27, List of Registers.
Section 3 MCU Operating Modes
2
C_2 bus mode register
2
C_0 bus mode register
Rev. 1.00 May 09, 2008 Page 69 of 954
REJ09B0462-0100