Timer Control Register (Tcr) - Renesas H8S/2368 Series Hardware Manual

10.3.1

Timer Control Register (TCR)

The TCR registers control the TCNT operation for each channel. The TPU has a total of six TCR
registers, one for each channel. TCR register settings should be made only when TCNT operation
is stopped.
Bit Bit Name Initial Value
7 CCLR2 0
6 CCLR1 0
5 CCLR0 0
4 CKEG1 0
3 CKEG0 0
2 TPSC2 0
1 TPSC1 0
0 TPSC0 0
Rev. 2.00, 05/03, page 380 of 820
R/W Description
R/W Counter Clear 2 to 0
R/W
These bits select the TCNT counter clearing source.
R/W
See tables 10.3 and 10.4 for details.
R/W Clock Edge 1 and 0
R/W
These bits select the input clock edge. When the
input clock is counted using both edges, the input
clock period is halved (e.g. φ/4 both edges = φ/2
rising edge). If phase counting mode is used on
channels 1, 2, 4, and 5, this setting is ignored and the
phase counting mode setting has priority. Internal
clock edge selection is valid when the input clock is
φ/4 or slower. This setting is ignored if the input clock
is φ/1, or when overflow/underflow of another channel
is selected.
00: Count at rising edge
01: Count at falling edge
1x: Count at both edges
Legend: x: Don't care
R/W Time Prescaler 2 to 0
R/W
These bits select the TCNT counter clock. The clock
R/W
source can be selected independently for each
channel. See tables 10.5 to 10.10 for details.