Timer Control Register (Tcr) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
10.3.1

Timer Control Register (TCR)

The TCR registers are 8-bit readable/writable registers that control the TCNT operation for each channel. This module
has a total of five TCR registers, one each for channels 0 to 4. TCR register settings should be conducted only when
TCNT operation is stopped.
Bit Bit Name
7 to 5 CCLR[2:0]
4, 3 CKEG[1:0]
2 to 0 TPSC[2:0]
[Legend]
x: Don't care
Table 10.4 CCLR0 to CCLR2 (Channels 0, 3, and 4)
Bit 7
Channel CCLR2
0, 3, 4 0
1
Note 1. Synchronous operation is set by setting the SYNC bit in TSYR to 1.
Note 2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the buffer register setting has priority, and
compare match/input capture does not occur.
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
Bit: 7 6
CCLR[2:0]
Initial value: 0 0
R/W: R/W R/W
Initial
Value R/W Description
000 R/W Counter Clear 0 to 2
These bits select the TCNT counter clearing source. See Table 10.4 and Table
10.5 for details.
00 R/W Clock Edge 0 and 1
These bits select the input clock edge. When the input clock is counted using
both edges, the input clock period is halved (e.g. P0φ/4 both edges = P0φ/2
rising edge). If phase counting mode is used on channels 1 and 2, this setting is
ignored and the phase counting mode setting has priority. Internal clock edge
selection is valid when the input clock is P0φ/4 or slower. When P0φ/1, or the
overflow/underflow of another channel is selected for the input clock, although
values can be written, counter operation compiles with the initial value.
00: Count at rising edge
01: Count at falling edge
1x: Count at both edges
000 R/W Time Prescaler 0 to 2
These bits select the TCNT counter clock. The clock source can be selected
independently for each channel. See Table 10.6 to Table 10.9 for details.
Bit 6 Bit 5
CCLR1 CCLR0 Description
0 0 TCNT clearing disabled
1 TCNT cleared by TGRA compare match/input capture
1 0 TCNT cleared by TGRB compare match/input capture
1 TCNT cleared by counter clearing for another channel performing synchronous
clearing/synchronous operation*
0 0 TCNT clearing disabled
1 TCNT cleared by TGRC compare match/input capture*
1 0 TCNT cleared by TGRD compare match/input capture*
1 TCNT cleared by counter clearing for another channel performing synchronous
clearing/synchronous operation*
5 4 3 2 1
CKEG[1:0] TPSC[2:0]
0 0 0 0 0
R/W R/W R/W R/W R/W
1
1
10. Multi-Function Timer Pulse Unit 2
0
0
R/W
2
2
10-8