Serial Timer Control Register (Stcr) - Renesas H8S/2100 Series Hardware Manual

3.2.3

Serial Timer Control Register (STCR)

STCR enables or disables register access, IIC operating mode, and on-chip flash memory, and
selects the input clock of the timer counter.
Initial
Bit Bit Name Value
7 IICX2 0
6 IICX1 0
5 IICX0 0
4 IICE 0
R/W Description
2
R/W I C Transfer Rate Select 2 to 0
R/W These bits control the IIC operation. These bits select
the transfer rate in master mode together with bits
R/W
CKS2 to CKS0 in the I
details on the transfer rate, see table 18.4.
2
R/W I C Master Enable
When the RELOCATE bit is cleared to 0, enables or
disables CPU access for IIC registers (ICCR, ICSR,
ICDR/SARX, ICMR/SAR, and ICRES), PWMX registers
(DADRAH/DACR, DADRAL, DADRBH/DACNTH, and
DADRBL/DACNTL), and SCI registers (SMR, BRR, and
SCMR).
0: SCI_1 registers are accessed in areas from
H'(FF)FF88 to H'(FF)FF89 and from H'(FF)FF8E to
H'(FF)FF8F.
SCI_2 registers are accessed in areas from
H'(FF)FFA0 to H'(FF)FFA1 and from H'(FF)FFA6 to
H'(FF)FFA7.
Access is prohibited in areas from H'(FF)FFD8 to
H'(FF)FFD9 and from H'(FF)FFDE to H'(FF)FFDF.
1: IIC_1 registers are accessed in areas from
H'(FF)FF88 to H'(FF)FF89 and from H'(FF)FF8E to
H'(FF)FF8F.
PWMX registers are accessed in areas from
H'(FF)FFA0 to H'(FF)FFA1 and from H'(FF)FFA6 to
H'(FF)FFA7.
IIC_0 registers are accessed in areas from
H'(FF)FFD8 to H'(FF)FFD9 and from H'(FF)FFDE to
H'(FF)FFDF.
ICRES is accessed in areas of H'(FF)FEE6
When the RELOCATE bit is set to 1, this bit is disabled.
For details, see section 3.2.4, System Control Register
3 (SYSCR3) and section 27, List of Registers.
Section 3 MCU Operating Modes
2
C bus mode register (ICMR). For
Rev. 1.00 Apr. 28, 2008 Page 71 of 994
REJ09B0452-0100