Serial Timer Control Register (Stcr); Iic Operation - Renesas H8S/2158 User Manual

3.2.3

Serial Timer Control Register (STCR)

STCR enables or disables register access, IIC operating mode, and on-chip flash memory, and
selects the input clock of the timer counter.
Bit Bit Name Initial Value
7 — 0
6 IICX1 0
5 IICX0 0
4 IICE 0
R/W Description
R/(W) Reserved
The initial value should not be changed.
R/W IIC Transfer Rate Select 1 and 0
R/W
These bits control the IIC operation. These bits select
a transfer rate in master mode together with bits
CKS2 to CKS0 in the I
For details on the transfer rate, see table 17.3. The
IICX0 bit controls IIC_0 and the IICX1 bit controls
IIC_1.
R/W IIC Master Enable
Enables or disables CPU access for IIC registers
(ICCR, ICSR, ICDR/SARX, ICMR/SAR), PWMX
registers (DADRAH/DACR, DADRAL,
DADRBH/DACNTH, DADRBL/DACNTL), and SCI
registers (SMR, BRR, SCMR).
0: SCI_1 registers are accessed in an area from
H'(FF)FF88 to H'(FF)FF89 and from H'(FF)FF8E
to H'(FF)FF8F.
SCI_2 registers are accessed in an area from
H'(FF)FFA0 to H'(FF)FFA1 and from H'(FF)FFA6
to H'(FF)FFA7.
SCI_0 registers are accessed in an area from
H'(FF)FFD8 to H'(FF)FFD9 and from H'(FF)FFDE
to H'(FF)FFDF.
1: IIC_1 registers are accessed in an area from
H'(FF)FF88 to H'(FF)FF89 and from H'(FF)FF8E
to H'(FF)FF8F.
PWMX registers are accessed in an area from
H'(FF)FFA0 to H'(FF)FFA1 and from H'(FF)FFA6
to H'(FF)FFA7.
IIC_0 registers are accessed in an area from
H'(FF)FFD8 to H'(FF)FFD9 and from H'(FF)FFDE
to H'(FF)FFDF.
Section 3 MCU Operating Modes
2
C bus mode register (ICMR).
Rev. 3.00 Jan 25, 2006 page 59 of 872
REJ09B0286-0300