Figure 2.16 State Transitions - Renesas H8SX/1500 Series Hardware Manual

Section 2 CPU
Reset state*
RES = high
RES = low
Exception-handling
Bus-released state
Interrupt
state
Bus
request
request
Request for exception End of exception
handling handling
Bus request End of bus request
End of
bus request
Program execution
Program stop state
state
SLEEP instruction
A transition to the reset state occurs whenever the RES signal goes low.
Note: *
A transition can also be made to the reset state when the watchdog timer
overflows.

Figure 2.16 State Transitions

Rev. 3.00 Mar. 14, 2006 Page 65 of 804
REJ09B0104-0300