Figure 2.16 State Transitions - Renesas H8SX/1520 Series Hardware Manual

32-bit cisc microcomputer
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RES = high
Exception-handling
state
End of exception
handling
handling
Program execution
state
A transition to the reset state occurs whenever the RES signal goes low.
Note: *
A transition can also be made to the reset state when the watchdog timer
overflows.

Figure 2.16 State Transitions

Reset state*
RES = low
Bus-released state
Interrupt
Bus
request
request
Bus request
End of
bus request
Program stop state
SLEEP instruction
Rev. 3.00 Mar. 14, 2006 Page 65 of 804
Section 2 CPU
End of bus request
REJ09B0104-0300

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