Internal Block Diagram - Renesas H8 Series Hardware Manual

Section 1 Overview
1.2

Internal Block Diagram

Figure 1.1 shows a block diagram of the H8/3644 Group.
P1 /TMOW
0
P1 /PWM
4
P1 /IRQ
5 1
P1 /IRQ
6 2
P1 /IRQ /TRGV
7 3
P2 /SCK
0 3
P2 /RXD
1
P2 /TXD
2
P3 /SCK
0 1
P3 /SI
1 1
P3 /SO
2 1
*
P9 /FV
0 PP
P9
1
P9
2
P9
3
P9
4
Note: * There is no P9
Rev. 6.00 Sep 12, 2006 page 6 of 526
REJ09B0326-0600
CPU
H8/300L
Data bus (lower)
ROM
Timer A
Timer B1
Watchdog
timer
A/D converter
Port B
function in the flash memory version.
0
Figure 1.1 Block Diagram
RAM
SCI1
SCI3
Timer X
Timer V
14-bit PWM
P8
7
P8 /FTID
6
P8 /FTIC
5
P8 /FTIB
4
P8 /FTIA
3
P8 /FTOB
2
P8 /FTOA
1
P8 /FTCI
0
P7
7
P7 /TMOV
6
P7 /TMCIV
5
P7 /TMRIV
4
P7
3
P6
7
P6
6
CMOS large-
P6
5
current port
P6
4
I = 10 mA
P6
OL
3
@V = 1V
P6
OL
2
P6
1
P6
0
P5 /INT
7 7
P5 /INT /TMIB
6 6
P5 /INT /ADTRG
5 5
P5 /INT
4 4
P5 /INT
3 3
P5 /INT
2 2
P5 /INT
1 1
P5 /INT
0 0