Interrupts; Operation Timing; Figure 8.9 Dtc Operation Timing (Example In Normal Mode Or Repeat Mode) - Renesas H8S Series Hardware Manual

Section 8 Data Transfer Controller (DTC)
8.5.5

Interrupts

An interrupt request is issued to the CPU when the DTC has completed the specified number of
data transfers, or a data transfer for which the DISEL bit was set to 1. In the case of interrupt
activation, the interrupt set as the activation source is generated. These interrupts to the CPU are
subject to CPU mask level and interrupt controller priority level control.
In the case of software activation, a software-activated data transfer end interrupt (SWDTEND) is
generated.
When the DISEL bit is 1 and one data transfer has been completed, or the specified number of
transfers have been completed, after data transfer ends the SWDTE bit is held at 1 and an
SWDTEND interrupt is generated. The interrupt handling routine will then clear the SWDTE bit
to 0.
When the DTC is activated by software, an SWDTEND interrupt is not generated during a data
transfer wait or during data transfer even if the SWDTE bit is set to 1.
8.5.6

Operation Timing

φ
DTC activation
request
DTC
request
Address

Figure 8.9 DTC Operation Timing (Example in Normal Mode or Repeat Mode)

Rev. 6.00 Mar 15, 2006 page 120 of 570
REJ09B0211-0600
Vector read
Transfer
information read
Data transfer
Read Write
Transfer
information write