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M16C/29 Group
14.2.1 SI/Oi Operation Timing
Figure 14.2.1.1 shows the SI/Oi operation timing
SI/Oi internal clock
CLKi output
Signal written to the
SiTRR register
S
i output
OUT
S
i input
IN
SiIC register
IR bit
i= 3, 4
Note 1: This diagram applies to the case where the SiC register bits are set as follows:
SMi2=0 (S
i output), SMi3=1 (S
OUT
rising edge of the transfer clock), SMi5=0 (LSB first) and SMi6=1 (internal clock)
Note 2: When the SMi6 bit = 1 (internal clock), the S
Note 3: If the SMi6 bit=0 (internal clock), the serial I/O starts sending or receiving data a maximum of 1.5 transfer clock cycles after writing to the
SiTRR register.
Figure 14.2.1.1. SI/Oi Operation Timing
14.2.2 CLK Polarity Selection
The SiC register's SMi4 bit allows selection of the polarity of the transfer clock. Figure 14.2.2.1 shows
the polarity of the transfer clock.
(1) When SiC register's SMi4 bit = "0"
CLK
i
S
INi
S
OUTi
(2) When SiC register's SMi4 bit = "1"
CLK
i
S
INi
S
OUTi
i=3 and 4
Note 1: This diagram applies to the case where the SiC register bits are set as follows:
SMi5=0 (LSB first) and SMi6=1 (internal clock)
Note 2: When the SMi6 bit=1 (internal clock), a high level is output from the CLKi
pin if not transferring data.
Note 3: When the SMi6 bit=1 (internal clock), a low level is output from the CLKi
pin if not transferring data.
Figure 14.2.2.1. Polarity of Transfer Clock
Rev.1.00 Nov 01,2004
REJ09B0101-0100Z
1.5 cycle (max)
(Note 3)
"H"
"L"
"H"
"L"
"H"
"L"
"H"
D
0
"L"
"H"
"L"
"1"
"0"
i output, CLKi function), SMi4=0 (transmit data output at the falling edge and receive data input at the
OUT
i pin is placed in the high-impedance state after the transfer finishes.
OUT
D0
D
D
D
1
2
3
D
D
D
D
0
1
2
3
D
D
D
D
0
1
2
3
D
D
D
D
0
1
2
3
page 212 of 402
D
D
D
1
2
3
D
D
D
D
4
5
6
7
D
D
D
D
4
5
6
7
D
D
D
D
4
5
6
7
D
D
D
D
4
5
6
7
14.2 SI/O 3 and SI/O 4
D
D
D
4
5
6
(Note 2)
(Note 3)
(Note 2)
D
7
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