Figure 12.3 Typical A/D Converter Operation Timing - Renesas H8/3847R Series Hardware Manual

8-bit single-chip microcomputer super low power
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Section 12 A/D Converter
6. The A/D interrupt handling routine ends.
If ADSF is set to 1 again afterward, A/D conversion starts and steps 2 to 6 take place.
Figures 12.4 and 12.5 show flow charts of procedures for using the A/D converter.
Interrupt
(IRRAD)
IENAD
A/D conversion starts
ADSF
Channel 1 (AN
)
Idle
1
operation state
ADRRH
ADRRL
Note:
( ) indicates instruction execution by software.
*

Figure 12.3 Typical A/D Converter Operation Timing

Rev. 6.00 Aug 04, 2006 page 426 of 680
REJ09B0145-0600
Set *
Set *
A/D conversion (1)
Idle
A/D conversion result (1)
Set *
A/D conversion (2)
Read conversion result
Idle
Read conversion result
A/D conversion result (2)

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