Timer Buffer Operation Transfer Mode Register (Tbtm) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
10.3.6

Timer Buffer Operation Transfer Mode Register (TBTM)

The TBTM registers are 8-bit readable/writable registers that specify the timing for transferring data from the buffer
register to the timer general register in PWM mode. This module has three TBTM registers, one each for channels 0, 3,
and 4.
Bit Bit Name
7 to 3 —
2 TTSE
1 TTSB
0 TTSA
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
Bit: 7 6
- -
Initial value: 0 0
R/W: R R
Initial
Value R/W Description
All 0 R Reserved
These bits are always read as 0. The write value should always be 0.
0 R/W Timing Select E
Specifies the timing for transferring data from TGRF_0 to TGRE_0 when they
are used together for buffer operation.
In channels 3 and 4, bit 2 is reserved. It is always read as 0 and the write value
should always be 0. Do not set this bit to 1 when PWM mode is not selected in
channel 0.
0: When compare match E occurs in channel 0
1: When TCNT_0 is cleared
0 R/W Timing Select B
Specifies the timing for transferring data from TGRD to TGRB in each channel
when they are used together for buffer operation. Do not set this bit to 1 when
PWM mode is not selected in any channels.
0: When compare match B occurs in each channel
1: When TCNT is cleared in each channel
0 R/W Timing Select A
Specifies the timing for transferring data from TGRC to TGRA in each channel
when they are used together for buffer operation. Do not set this bit to 1 when
PWM mode is not selected in any channels.
0: When compare match A occurs in each channel
1: When TCNT is cleared in each channel
5 4 3 2 1
- - - TTSE TTSB
0 0 0 0 0
R R R R/W R/W
10. Multi-Function Timer Pulse Unit 2
0
TTSA
0
R/W
10-36