Buffer Operation; Figure 9.13 Compare Match Buffer Operation; Table 9.31 Register Combinations In Buffer Operation - Renesas H8SX/1520 Series Hardware Manual

9.4.3

Buffer Operation

Buffer operation, provided for channels 0 and 3, enables TGRC and TGRD to be used as buffer
registers.
Buffer operation differs depending on whether TGR has been designated as an input capture
register or a compare match register.
Table 9.31 shows the register combinations used in buffer operation.

Table 9.31 Register Combinations in Buffer Operation

Channel
0
3
• When TGR is an output compare register
When a compare match occurs, the value in the buffer register for the corresponding channel is
transferred to the timer general register.
This operation is illustrated in figure 9.13.
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Timer General Register
TGRA_0
TGRB_0
TGRA_3
TGRB_3
Buffer register

Figure 9.13 Compare Match Buffer Operation

Compare match signal
Timer general
Comparator
register
Section 9 16-Bit Timer Pulse Unit (TPU)
Buffer Register
TGRC_0
TGRD_0
TGRC_3
TGRD_3
TCNT
Rev. 3.00 Mar. 14, 2006 Page 307 of 804
REJ09B0104-0300