Buffer Operation; Figure 10.11 Example Of Synchronous Operation; Table 10.28 Register Combinations In Buffer Operation - Renesas H8S/2368 Series Hardware Manual

TCNT0 to TCNT2 values
TGRB_0
TGRB_1
TGRA_0
TGRB_2
TGRA_1
TGRA_2
H'0000
TIOCA_0
TIOCA_1
TIOCA_2
10.4.3

Buffer Operation

Buffer operation, provided for channels 0 and 3, enables TGRC and TGRD to be used as buffer
registers.
Buffer operation differs depending on whether TGR has been designated as an input capture
register or a compare match register.
Table 10.28 shows the register combinations used in buffer operation.

Table 10.28 Register Combinations in Buffer Operation

Channel
0
3
• When TGR is an output compare register
When a compare match occurs, the value in the buffer register for the corresponding channel is
transferred to the timer general register.
This operation is illustrated in figure 10.12.
Rev. 2.00, 05/03, page 418 of 820
Synchronous clearing by TGRB_0 compare match

Figure 10.11 Example of Synchronous Operation

Timer General Register
TGRA_0
TGRB_0
TGRA_3
TGRB_3
Buffer Register
TGRC_0
TGRD_0
TGRC_3
TGRD_3
Time