Buffer Operation - Renesas H8S Series Hardware Manual

16-bit single-chip microcomputer

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Buffer Operation

Buffer operation, provided for channels 0 and 3, enables TGRC and TGRD to be used as buffer registers.

Buffer operation differs depending on whether TGR has been designated as an input capture register or as a compare

match register.

Table 10-5 shows the register combinations used in buffer operation.

Table 10-5 Register Combinations in Buffer Operation

• When TGR is an output compare register

When a compare match occurs, the value in the buffer register for the corresponding channel is transferred to the timer

general register.

This operation is illustrated in figure 10-16.

Buffer register

• When TGR is an input capture register

When input capture occurs, the value in TCNT is transferred to TGR and the value previously held in the timer general

This operation is illustrated in figure 10-17.

Input capture

Buffer register

Timer General Register

Compare match signal

Timer general

Figure 10-16 Compare Match Buffer Operation

Timer general

Figure 10-17 Input Capture Buffer Operation

Buffer Register

Rev.6.00 Oct.28.2004 page 379 of 1016

REJ09B0138-0600H