Buffer Operation; Figure 10.12 Compare Match Buffer Operation; Table 10.28 Register Combinations In Buffer Operation - Renesas H8S Series Hardware Manual

16-bit single-chip microcomputer

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Buffer Operation

Buffer operation, provided for channels 0 and 3, enables TGRC and TGRD to be used as buffer

Buffer operation differs depending on whether TGR has been designated as an input capture

Table 10.28 shows the register combinations used in buffer operation.

• When TGR is an output compare register

When a compare match occurs, the value in the buffer register for the corresponding channel is

transferred to the timer general register.

This operation is illustrated in figure 10.12.

Buffer register

Timer General Register

Compare match signal

Timer general

Section 10 16-Bit Timer Pulse Unit (TPU)

Buffer Register

Rev. 6.00 Mar 15, 2006 page 205 of 570

REJ09B0211-0600