Table 12.11 Tiorl_0 (Channel 0) - Renesas H8S/2437 Hardware Manual

Table 12.11 TIORL_0 (Channel 0)

Bit 7 Bit 6
IOD3 IOD2
0 0
1
1 0
1
[Legend] x: Don't care
Notes: 1. When bits TPSC2 to TPSC0 in TCR_1 are set to B'000 and φ/1 is used as the TCNT_1
count clock, this setting is invalid and input capture is not generated.
2. When the BFB bit in TMDR_0 is set to 1 and TGRD_0 is used as a buffer register, this
setting is invalid and input capture/output compare is not generated.
Bit 5 Bit 4
IOD1 IOD0
0 0
1
1 0
1
0 0
1
1 0
1
0 0
1
×
1
× ×
TGRD_0
Function TIOCD0 Pin Function
Output Output disabled
compare
Initial output is 0 output
2
register*
0 output at compare match
Initial output is 0 output
1 output at compare match
Initial output is 0 output
Toggle output at compare match
Output disabled
Initial output is 1 output
0 output at compare match
Initial output is 1 output
1 output at compare match
Initial output is 1 output
Toggle output at compare match
Input capture Capture input source is TIOCD0 pin
2
register* Input capture at rising edge
Capture input source is TIOCD0 pin
Input capture at falling edge
Capture input source is TIOCD0 pin
Input capture at both edges
Capture input source is channel
1/count clock
Input capture at TCNT_1 count-
up/count-down*
Description
1
Rev. 1.00, 09/03, page 313 of 704