Timer Interrupt Enable Register (Tier) - Renesas F-ZTAT H8 Series Hardware Manual

10.2.13 Timer Interrupt Enable Register (TIER)

TIER is an 8-bit register. The ITU has five TIERs, one in each channel.
Channel Abbreviation
0 TIER0
1 TIER1
2 TIER2
3 TIER3
4 TIER4
Bit 7
—
Initial value 1
Read/Write —
Each TIER is an 8-bit readable/writable register that enables and disables overflow interrupt
requests and general register compare match and input capture interrupt requests.
TIER is initialized to H'F8 by a reset and in standby mode.
Bits 7 to 3—Reserved: Read-only bits, always read as 1.
Function
Enables or disables interrupt requests.
6 5 4
— — —
1 1 1
— — —
Reserved bits
Overflow interrupt enable
Enables or disables OVF
interrupts
Section 10 16-Bit Integrated Timer Unit (ITU)
3 2
— OVIE
1 0
— R/W
Input capture/compare match
interrupt enable B
Enables or disables IMFB interrupts
Input capture/compare match
interrupt enable A
Enables or disables IMFA
interrupts
Rev. 7.00 Sep 21, 2005 page 347 of 878
1 0
IMIEB IMIEA
0 0
R/W R/W
REJ09B0259-0700