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9.3.4
Timer Interrupt Enable Register (TIER)
TIER controls enabling or disabling of interrupt requests for each channel. The TPU has six TIER
registers, one for each channel.
Bit
7
Bit Name
TTGE
Initial Value
0
R/W
R/W
Bit
Bit Name
7
TTGE
6
5
TCIEU
4
TCIEV
6
5
TCIEU
1
0
R
R/W
Initial
value
R/W
Description
0
R/W
A/D Conversion Start Request Enable
Enables/disables generation of A/D conversion start
requests by TGRA input capture/compare match.
0: A/D conversion start request generation disabled
1: A/D conversion start request generation enabled
1
R
Reserved
This is a read-only bit and cannot be modified.
0
R/W
Underflow Interrupt Enable
Enables/disables interrupt requests (TCIU) by the TCFU
flag when the TCFU flag in TSR is set to 1 in channels 1,
2, 4, and 5.
In channels 0 and 3, bit 5 is reserved. It is always read as
0 and cannot be modified.
0: Interrupt requests (TCIU) by TCFU disabled
1: Interrupt requests (TCIU) by TCFU enabled
0
R/W
Overflow Interrupt Enable
Enables/disables interrupt requests (TCIV) by the TCFV
flag when the TCFV flag in TSR is set to 1.
0: Interrupt requests (TCIV) by TCFV disabled
1: Interrupt requests (TCIV) by TCFV enabled
Section 9 16-Bit Timer Pulse Unit (TPU)
4
3
TCIEV
TGIED
0
0
R/W
R/W
Rev.2.00 Jun. 28, 2007 Page 337 of 666
2
1
TCIEC
TGIEB
0
0
R/W
R/W
REJ09B0311-0200
0
TGIEA
0
R/W
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