Timer Interrupt Enable Register (Tier) - Renesas H8S Series Hardware Manual

10.2.4

Timer Interrupt Enable Register (TIER)

Channel 0: TIER0
Channel 3: TIER3
Bit : 7
TTGE
Initial value : 0
R/W : R/W
Channel 1: TIER1
Channel 2: TIER2
Channel 4: TIER4
Channel 5: TIER5
Bit : 7
TTGE
Initial value : 0
R/W : R/W
The TIER registers are 8-bit registers that control enabling or disabling of interrupt requests for each channel. The TPU
has six TIER registers, one for each channel. The TIER registers are initialized to H'40 by a reset, and in hardware standby
mode.
Bit 7—A/D Conversion Start Request Enable (TTGE): Enables or disables generation of A/D conversion start requests
by TGRA input capture/compare match.
Bit 7
TTGE
0
1
Bit 6—Reserved: This bit cannot be modified and is always read as 1.
Bit 5—Underflow Interrupt Enable (TCIEU): Enables or disables interrupt requests (TCIU) by the TCFU flag when
the TCFU flag in TSR is set to 1 in channels 1 and 2.
In channels 0 and 3, bit 5 is reserved. It is always read as 0 and cannot be modified.
Bit 5
TCIEU
0
1
6 5
— —
1 0
— —
6 5
— TCIEU
1 0
— R/W
Description
A/D conversion start request generation disabled
A/D conversion start request generation enabled
Description
Interrupt requests (TCIU) by TCFU disabled
Interrupt requests (TCIU) by TCFU enabled
4 3 2
TCIEV TGIED TGIEC
0 0 0
R/W R/W R/W
4 3 2
TCIEV — —
0 0 0
R/W — —
1 0
TGIEB TGIEA
0 0
R/W R/W
1 0
TGIEB TGIEA
0 0
R/W R/W
(Initial value)
(Initial value)
Rev.6.00 Oct.28.2004 page 361 of 1016
REJ09B0138-0600H