Timer Interrupt Enable Register (Tier) - Renesas H8SX/1520 Series Hardware Manual

Section 9 16-Bit Timer Pulse Unit (TPU)
9.3.4

Timer Interrupt Enable Register (TIER)

TIER controls enabling or disabling of interrupt requests for each channel. The TPU has six TIER
registers, one for each channel.
Bit
Bit Name TTGE*
Initial Value
R/W
Note: * Bit 7 in TIER for unit 1 is a reserved bit and is always read as 0. The write value should always be 0.
Bit Bit Name
7 TTGE*

6
5 TCIEU
4 TCIEV
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7 6
— TCIEU
0 1
R/W R R/W
Initial
value R/W
0 R/W
1 R
0 R/W
0 R/W
5 4 3
TCIEV TGIED
0 0 0
R/W R/W
Description
A/D Conversion Start Request Enable
Enables/disables generation of A/D conversion start
requests by TGRA input capture/compare match.
0: A/D conversion start request generation disabled
1: A/D conversion start request generation enabled
Reserved
This is a read-only bit and cannot be modified.
Underflow Interrupt Enable
Enables/disables interrupt requests (TCIU) by the TCFU
flag when the TCFU flag in TSR is set to 1 in channels 1,
2, 4, and 5.
In channels 0 and 3, bit 5 is reserved. It is a read-only bit
and cannot be modified.
0: Interrupt requests (TCIU) by TCFU disabled
1: Interrupt requests (TCIU) by TCFU enabled
Overflow Interrupt Enable
Enables/disables interrupt requests (TCIV) by the TCFV
flag when the TCFV flag in TSR is set to 1.
0: Interrupt requests (TCIV) by TCFV disabled
1: Interrupt requests (TCIV) by TCFV enabled
2 1
TGIEC TGIEB TGIEA
0 0
R/W R/W
0
0
R/W