Timer Interrupt Enable Register (Tier) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
10.3.4

Timer Interrupt Enable Register (TIER)

The TIER registers are 8-bit readable/writable registers that control enabling or disabling of interrupt requests for each
channel. This module has six TIER registers, two for channel 0 and one each for channels 1 to 4.
• TIER_0, TIER_1, TIER_2, TIER_3, TIER_4
Bit Bit Name
7 TTGE
6 TTGE2
5 TCIEU
4 TCIEV
3 TGIED
2 TGIEC
1 TGIEB
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
Bit: 7 6
TTGE TTGE2 TCIEU TCIEV TGIED TGIEC TGIEB TGIEA
Initial value: 0 0
R/W: R/W R/W
Initial
Value R/W Description
0 R/W A/D Conversion Start Request Enable
Enables or disables generation of A/D conversion start requests by TGRA input
capture/compare match.
0: A/D converter start request generation disabled
1: A/D converter start request generation enabled
0 R/W A/D Conversion Start Request Enable 2
Enables or disables generation of A/D conversion start requests by TCNT_4
underflow (trough) in complementary PWM mode.
In channels 0 to 3, bit 6 is reserved. It is always read as 0 and the write value
should always be 0.
0: A/D conversion start request generation by TCNT_4 underflow (trough)
disabled
1: A/D conversion start request generation by TCNT_4 underflow (trough)
enabled
0 R/W Underflow Interrupt Enable
Enables or disables interrupt requests (TCIU) by the TCFU flag when the TCFU
flag in TSR is set to 1 in channels 1 and 2.
In channels 0, 3, and 4, bit 5 is reserved. It is always read as 0 and the write
value should always be 0.
0: Interrupt requests (TCIU) by TCFU disabled
1: Interrupt requests (TCIU) by TCFU enabled
0 R/W Overflow Interrupt Enable
Enables or disables interrupt requests (TCIV) by the TCFV flag when the TCFV
flag in TSR is set to 1.
0: Interrupt requests (TCIV) by TCFV disabled
1: Interrupt requests (TCIV) by TCFV enabled
0 R/W TGR Interrupt Enable D
Enables or disables interrupt requests (TGID) by the TGFD bit when the TGFD
bit in TSR is set to 1 in channels 0, 3, and 4.
In channels 1 and 2, bit 3 is reserved. It is always read as 0 and the write value
should always be 0.
0: Interrupt requests (TGID) by TGFD bit disabled
1: Interrupt requests (TGID) by TGFD bit enabled
0 R/W TGR Interrupt Enable C
Enables or disables interrupt requests (TGIC) by the TGFC bit when the TGFC
bit in TSR is set to 1 in channels 0, 3, and 4.
In channels 1 and 2, bit 2 is reserved. It is always read as 0 and the write value
should always be 0.
0: Interrupt requests (TGIC) by TGFC bit disabled
1: Interrupt requests (TGIC) by TGFC bit enabled
0 R/W TGR Interrupt Enable B
Enables or disables interrupt requests (TGIB) by the TGFB bit when the TGFB
bit in TSR is set to 1.
0: Interrupt requests (TGIB) by TGFB bit disabled
1: Interrupt requests (TGIB) by TGFB bit enabled
5 4 3 2 1
0 0 0 0 0
R/W R/W R/W R/W R/W
10. Multi-Function Timer Pulse Unit 2
0
0
R/W
10-31