Data Transfer With Interrupt Request Signals; Handling Interrupt Request Signals As Sources For Cpu Interrupt But Not Direct Memory Access Controller Activating; Handling Interrupt Request Signals As Sources For Activating Direct Memory Access Controller But Not Cpu Interrupt - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
7.7

Data Transfer with Interrupt Request Signals

Interrupt request signals can be used to activate the direct memory access controller and transfer data.
Interrupt sources for which the direct memory access controller is designated as the destination by DMA extension
resource selectors 0 to 7 are masked and requests from them are not input to the interrupt controller.
Figure 7.4 shows a block diagram of interrupt control. For details, see section 9, Direct Memory Access Controller.
Interrupt source flag clearing
(by the direct memory
access controller)
Interrupt source
Figure 7.4 Interrupt Control Block Diagram
7.7.1 Handling Interrupt Request Signals as Sources for CPU Interrupt
but Not Direct Memory Access Controller Activating
1. Do not select direct memory access controller activating sources.
2. When interrupts occur, interrupt requests are sent to the CPU.
3. The CPU clears the interrupt source and performs the necessary processing in the interrupt exception service
routine.
7.7.2 Handling Interrupt Request Signals as Sources for Activating
Direct Memory Access Controller but Not CPU Interrupt
1. Select direct memory access controller activating sources.
2. Activating sources are applied to the direct memory access controller when interrupts occur.
3. The direct memory access controller clears the interrupt sources when starting transfer.
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
Direct memory access controller
Activating
source selected
Activating
source
selection
logic
Activating source not selected
Interrupt source
(not specified as a direct memory access controller activating source)
CPU interrupt source
Interrupt
controller
7. Interrupt Controller
Data
transfer
control
logic
CPU
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