14.10.5 Relation Between Writes To Tdr And The Tdre Flag; 14.10.6 Restrictions On Use Of Dmac* Or Dtc; 14.10.7 Operation In Case Of Mode Transition; Figure 14.35 Example Of Synchronous Transmission Using Dtc - Renesas H8S/2368 Series Hardware Manual

14.10.5 Relation between Writes to TDR and the TDRE Flag

The TDRE flag in SSR is a status flag that indicates that transmit data has been transferred from
TDR to TSR. When the SCI transfers data from TDR to TSR, the TDRE flag is set to 1.
Data can be written to TDR regardless of the state of the TDRE flag. However, if new data is
written to TDR when the TDRE flag is cleared to 0, the data stored in TDR will be lost since it has
not yet been transferred to TSR. It is therefore essential to check that the TDRE flag is set to 1
before writing transmit data to TDR.

14.10.6 Restrictions on Use of DMAC* or DTC

• When an external clock source is used as the serial clock, the transmit clock should not be
input until at least five φ clock cycles after TDR is updated by the DMAC* or DTC. Abnormal
operation may occur if the transmit clock is input within 4 φ clocks after TDR is updated.
(figure 14.35)
• When RDR is read by the DMAC * or DTC, be sure to set the activation source to the relevant
SCI receive-data-full interrupt (RXI).
Note: * Not supported by the H8S/2366.
SCK
TDRE
Serial data
Note: When operating on an external clock, set t > 4 clocks.

Figure 14.35 Example of Synchronous Transmission Using DTC

14.10.7 Operation in Case of Mode Transition

• Transmission
Operation should be stopped (by clearing TE, TIE, and TEIE to 0) before making a module
stop mode or software standby mode transition. TSR, TDR, and SSR are reset. The output pin
states in module stop mode or software standby mode depend on the port settings, and become
high-level output after the relevant mode is cleared. If a transition is made during
transmission, the data being transmitted will be undefined.
Rev. 2.00, 05/03, page 584 of 820
t
LSB
D0 D1 D2 D3 D4 D5 D6 D7