Renesas M16C Series Manuals

Manuals and User Guides for Renesas M16C Series. We have 4 Renesas M16C Series manuals available for free PDF download: Hardware User Manual, User Manual, Reference Book

Renesas M16C Series Hardware User Manual (1031 pages)

Brand: Renesas | Category: Microcontrollers | Size: 12 MB

General Precautions in the Handling of MPU/MCU Products
3
About this Manual
4
Numbers and Symbols
5
Abbreviations and Acronyms
7
Table of Contents
8
Quick Reference
29
Overview
46
Features
46
Applications
46
Specifications
47
Product List
53
Block Diagrams
57
Pin Assignments
60
Pin Functions
69
Signal Name
70
Central Processing Unit (CPU)
72
Data Registers (R0, R1, R2, and R3)
73
Address Registers (A0 and A1)
73
Frame Base Register (FB)
73
Interrupt Table Register (INTB)
73
Program Counter (PC)
73
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
73
Static Base Register (SB)
73
Flag Register (FLG)
73
Carry Flag (C Flag)
73
Debug Flag (D Flag)
73
Interrupt Enable Flag (I Flag)
74
Stack Pointer Select Flag (U Flag)
74
Processor Interrupt Priority Level (IPL)
74
Reserved Areas
74
Memory
75
Special Function Registers (Sfrs)
77
Sfrs
77
Notes on Sfrs
124
Register Settings
124
Protection
126
Introduction
126
Register
126
Protect Register (PRCR)
126
Notes on Protection
128
Resets
129
Introduction
129
Registers
131
Processor Mode Register 0 (PM0)
131
Reset Source Determine Register (RSTFR)
132
Optional Function Select Area
133
Optional Function Select Address 1 (OFS1)
133
Operations
135
Status after Reset
135
Hardware Reset
137
Power-On Reset Function
138
Voltage Monitor 0 Reset
139
Voltage Monitor 2 Reset
139
Oscillator Stop Detect Reset
139
Watchdog Timer Reset
139
Software Reset
140
Notes on Resets
141
Power Supply Rising Gradient
141
Power-On Reset
141
OSDR Bit (Oscillation Stop Detect Reset Detect Flag)
141
Hardware Reset When VCC < Vdet0
141
Voltage Detector
142
Introduction
142
Registers
143
Voltage Detector 2 Flag Register (VCR1)
144
Voltage Detector Operation Enable Register (VCR2)
145
Voltage Monitor Function Select Register (VWCE)
146
Voltage Detector 2 Level Select Register (VD2LS)
147
Voltage Monitor 0 Control Register (VW0C)
148
Voltage Monitor 2 Control Register (VW2C)
149
Optional Function Select Area
151
Optional Function Select Address 1 (OFS1)
151
Operations
152
Digital Filter
152
Voltage Detector 0
153
Voltage Detector 2
155
Monitoring Vdet2
155
Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset
156
Interrupts
158
Clock Generator
159
Introduction
159
Registers
161
System Clock Control Register 0 (CM0)
162
System Clock Control Register 1 (CM1)
164
Oscillation Stop Detection Register (CM2)
166
Peripheral Clock Select Register (PCLKR)
168
PLL Control Register 0 (PLC0)
169
Processor Mode Register 2 (PM2)
170
40 Mhz On-Chip Oscillator Control Register 0 (FRA0)
171
40 Mhz On-Chip Oscillator Control Register 2 (FRA2)
172
Clocks Generated by Clock Generators
173
Main Clock
173
PLL Clock
174
Foco40M
175
Foco-F
175
125 Khz On-Chip Oscillator Clock (Foco-S)
175
Sub Clock (Fc)
176
CPU Clock and Peripheral Function Clocks
177
CPU Clock and BCLK
177
Peripheral Function Clocks (F1, Foco40M, Foco-F, Foco-S, Fc32, Fc, Main Clock)
177
Clock Output Function
179
System Clock Protection Function
179
Oscillator Stop/Restart Detect Function
180
Operation When CM27 Bit Is 0 (Oscillator Stop Detect Reset)
180
Operation When CM27 Bit Is 1 (Oscillator Stop/Restart Detect Interrupt)
181
Using the Oscillator Stop/Restart Detect Function
182
Interrupt
182
Notes on Clock Generator
183
Oscillator Using a Crystal or a Ceramic Resonator
183
Noise Countermeasure
184
CPU Clock
185
Oscillator Stop/Restart Detect Function
185
PLL Frequency Synthesizer
186
Power Control
187
Introduction
187
Registers
187
Flash Memory Control Register 0 (FMR0)
188
Flash Memory Control Register 2 (FMR2)
189
Clock
191
Normal Operating Mode
191
Low Power Mode
192
Clock Mode Transition Procedure
195
Wait Mode
198
Stop Mode
200
Entering Stop Mode
200
Exiting Stop Mode
201
Power Control in Flash Memory
202
Stopping Flash Memory
202
Reading Flash Memory
203
Reducing Power Consumption
205
Ports
205
A/D Converter
205
D/A Converter
205
Stopping Peripheral Functions
205
Switching the Oscillation-Driving Capacity
205
Notes on Power Control
206
CPU Clock
206
Wait Mode
206
Stop Mode
206
Low Current Consumption Read Mode
207
Slow Read Mode
207
10. Processor Mode
208
Introduction
208
Registers
209
Processor Mode Register 1 (PM1)
209
Program 2 Area Control Register (PRG2C)
210
Flash Memory Control Register 1 (FMR1)
211
Software Wait
212
Bus Hold
212
11. Programmable I/O Ports
213
Introduction
213
I/O Ports and Pins
214
Registers
222
NMI Digital Debounce Register (NDDR)
223
P1_7 Digital Debounce Register (P17DDR)
223
Pull-Up Control Register 0 (PUR0)
224
Pull-Up Control Register 1 (PUR1)
224
Pull-Up Control Register 2 (PUR2)
225
Port Control Register (PCR)
226
Input Threshold Select Register 0 (VLT0)
227
Input Threshold Select Register 1 (VLT1)
228
Input Threshold Select Register 2 (VLT2)
228
Pin Assignment Control Register (PACR)
229
Port Pi Register (Pi) (I = 0 to 10)
230
Port Pi Direction Register (Pdi) (I = 0 to 10)
231
Peripheral Function I/O
232
Peripheral Function I/O and Port Direction Bits
232
Priority Level of Peripheral Function I/O
232
Digital Debounce Filters
233
Unassigned Pin Handling
235
Notes on Programmable I/O Ports
236
Pin Assignment Control
236
Influence of SD
236
Input Voltage Threshold
236
12. Interrupts
237
Introduction
237
Registers
238
Processor Mode Register 2 (PM2)
240
Interrupt Control Register 1
241
S4TIC/RTCCIC, S4RIC, C0WIC,S3TIC/C0EIC, RTCTIC/C1EIC, C0RIC, C1RIC, C0TIC, C1TIC, C0FRIC, C1FRIC, C0FTIC, C1FTIC, ICOC0IC, ICOCH0IC, ICOC1IC/IICIC, ICOCH1IC/SCLDAIC, ICOCH2IC to ICOCH3IC, BTIC)
241
(INT7IC/SS0IC, INT6IC/LIN0IC, INT3IC, INT5IC, INT4IC, INT0IC to INT2IC)
242
Interrupt Source Select Register 4 (IFSR4A)
244
Interrupt Source Select Register 3 (IFSR3A)
245
Interrupt Source Select Register 2 (IFSR2A)
246
Interrupt Source Select Register (IFSR)
247
Address Match Interrupt Enable Register (AIER)
248
Address Match Interrupt Enable Register 2 (AIER2)
248
Address Match Interrupt Register I (Rmadi) (I = 0 to 3)
249
NMI Digital Debounce Register (NDDR)
250
P1_7 Digital Debounce Register (P17DDR)
250
Types of Interrupts
251
Software Interrupts
252
Undefined Instruction Interrupt
252
Overflow Interrupt
252
BRK Interrupt
252
INT Instruction Interrupt
252
Hardware Interrupts
253
Special Interrupts
253
NMI Interrupt
253
Peripheral Function Interrupts
253
Interrupts and Interrupt Vectors
254
Fixed Vector Tables
254
Relocatable Vector Tables
255
Interrupt Control
257
Maskable Interrupt Control
257
Interrupt Sequence
258
Interrupt Response Time
259
Variation of IPL When Interrupt Request Is Accepted
259
Saving Registers
260
Returning from an Interrupt Routine
261
Interrupt Priority
261
Interrupt Priority Level Select Circuit
261
Multiple Interrupts
263
INT Interrupt
263
NMI Interrupt
264
12.10 Key Input Interrupt
264
12.11 Address Match Interrupt
265
12.12 Non-Maskable Interrupt Source Discrimination
266
12.13 Notes on Interrupts
267
12.13.1 Reading Address 00000H
267
12.13.2 SP Setting
267
12.13.3 NMI Interrupt
267
12.13.4 Changing an Interrupt Source
268
12.13.5 Rewriting the Interrupt Control Register
269
12.13.6 Instruction to Rewrite the Interrupt Control Register
269
12.13.7 INT Interrupt
270
13. Watchdog Timer
271
Introduction
271
Registers
273
Voltage Monitor 2 Control Register (VW2C)
274
Count Source Protection Mode Register (CSPR)
275
Watchdog Timer Refresh Register (WDTR)
275
Watchdog Timer Start Register (WDTS)
276
Watchdog Timer Control Register (WDC)
276
Optional Function Select Area
277
Optional Function Select Address 1 (OFS1)
277
Optional Function Select Address 2 (OFS2)
278
Operations
279
Refresh Operation Period
279
Count Source Protection Mode Disabled
280
Count Source Protection Mode Enabled
281
Interrupts
282
Notes on the Watchdog Timer
283
14. Dmac
284
Introduction
284
Registers
286
Dmai Source Pointer (Sari) (I = 0 to 3)
287
Dmai Destination Pointer (Dari) (I = 0 to 3)
287
Dmai Transfer Counter (Tcri) (I = 0 to 3)
288
Dmai Control Register (Dmicon) (I = 0 to 3)
289
Dmai Source Select Register (Dmisl) (I = 0 to 3)
290
Operations
293
DMA Enabled
293
DMA Request
293
Transfer Cycles
294
DMAC Transfer Cycles
296
Single Transfer Mode
297
Repeat Transfer Mode
298
Channel Priority and DMA Transfer Timing
299
Interrupts
300
Notes on DMAC
301
Write to the DMAE Bit in the Dmicon Register (I = 0 to 3)
301
Changing the DMA Request Source
301
15. Timer a
302
Introduction
302
Registers
305
Peripheral Clock Select Register (PCLKR)
306
Clock Prescaler Reset Flag (CPSRF)
306
Timer AB Division Control Register 0 (TCKDIVC0)
307
Timer a Count Source Select Register I (Tacsi) (I = 0 to 2)
308
16-Bit Pulse Width Modulation Mode Function Select Register (PWMFS)
309
Timer a Waveform Output Function Select Register (TAPOFS)
310
Timer a Output Waveform Change Enable Register (TAOW)
311
Timer Ai Register (Tai) (I = 0 to 4)
312
Event Counter Mode
312
One-Shot Timer Mode
312
Timer Ai-1 Register (Tai1) (I = 1, 2, 4)
313
Count Start Flag (TABSR)
313
One-Shot Start Flag (ONSF)
314
Trigger Select Register (TRGSR)
315
Increment/Decrement Flag (UDF)
316
Timer Ai Mode Register (Taimr) (I = 0 to 4)
317
Operations
318
Common Operations
318
Count Source
319
Timer Mode
320
Event Counter Mode (When Not Using Two-Phase Pulse Signal Processing)
324
Event Counter Mode (When Processing Two-Phase Pulse Signal)
328
Normal Processing
331
One-Shot Timer Mode
333
Pulse Width Modulation (PWM) Mode
337
Programmable Output Mode (Timers A1, A2, and A4)
342
Interrupts
346
Notes on Timer a
347
Common Notes on Multiple Modes
347
Timer a (Timer Mode)
348
Timer a (Event Counter Mode)
348
Timer a (One-Shot Timer Mode)
348
Changing Operating Modes
348
Timer a (Pulse Width Modulation Mode)
349
Timer a (Programmable Output Mode)
350
Changing the Operating Mode
350
16. Timer B
351
Introduction
351
Registers
354
Peripheral Clock Select Register (PCLKR)
355
Clock Prescaler Reset Flag (CPSRF)
355
Timer Bi Register (Tbi) (I = 0 to 5)
356
Event Counter Mode
356
Timer Bi-1 Register (Tbi1) (I = 0 to 5)
357
Pulse Period/Pulse Width Measurement Mode Function Select Register I (Ppwfsi) (I = 1, 2)
358
Timer B Count Source Select Register I (Tbcsi) (I = 0 to 3)
359
Timer AB Division Control Register 0 (TCKDIVC0)
360
Count Start Flag (TABSR) Timer B3/B4/B5 Count Start Flag (TBSR)
361
Timer Bi Mode Register (Tbimr) (I = 0 to 5)
362
Operations
363
Common Operations
363
Timer Mode
365
Event Counter Mode
367
Pulse Period/Pulse Width Measurement Modes
370
Interrupts
375
Notes on Timer B
376
Common Notes on Multiple Modes
376
Timer B (Timer Mode)
376
Timer B (Event Counter Mode)
376
Timer B (Pulse Period/Pulse Width Measurement Modes)
377
Pulse Period Measurement Mode
377
Pulse Width Measurement Mode
377
17. Three-Phase Motor Control Timer Function
378
Introduction
378
Registers
382
Timer B2 Register (TB2)
383
Timer Ai, Ai-1 Register (Tai, Tai1) (I = 1, 2, 4)
383
Three-Phase PWM Control Register 0 (INVC0)
384
Three-Phase PWM Control Register 1 (INVC1)
386
Three-Phase Output Buffer Register I (Idbi) (I = 0, 1)
388
Dead Time Timer (DTT)
388
Timer B2 Interrupt Generation Frequency Set Counter (ICTB2)
389
Timer B2 Special Mode Register (TB2SC)
390
Position-Data-Retain Function Control Register (PDRF)
391
Port Function Control Register (PFCR)
392
Three-Phase Protect Control Register (TPRC)
392
Operations
393
Common Operations in Multiple Modes
393
Dead Time Control
394
Triangular Wave Modulation Three-Phase Mode 0
399
Triangular Wave Modulation Three-Phase Mode 1
404
Sawtooth Wave Modulation Mode
411
Interrupts
416
Timer B2 Interrupt
416
Timer A1, A2, and A4 Interrupts
416
Notes on Three-Phase Motor Control Timer Function
417
Timer a and Timer B
417
Influence of SD
417
18. Timer S
418
Introduction
418
Registers
422
Time Measurement Register J (G1Tmj) (J = 0 to 7)
424
Waveform Generation Register J (G1Poj) (J = 0 to 7)
425
Waveform Generation Control Register J (G1Pocrj) (J = 0 to 7)
426
Time Measurement Control Register J (G1Tmcrj) (J = 0 to 7)
428
Base Timer Register (G1BT)
430
Base Timer Control Register 0 (G1BCR0)
431
Base Timer Control Register 1 (G1BCR1)
432
Time Measurement Prescaler Register J (G1Tprj) (J = 6 and 7)
433
Function Enable Register (G1FE)
433
Function Select Register (G1FS)
434
Base Timer Reset Register (G1BTRR)
435
Count Source Divide Register (G1DV)
435
Waveform Output Master Enable Register (G1OER)
436
Timer S I/O Control Register 0 (G1IOR0)
437
Timer S I/O Control Register 1 (G1IOR1)
438
Interrupt Request Register (G1IR)
439
Interrupt Enable Register 0 (G1IE0)
440
Interrupt Enable Register 1 (G1IE1)
441
Operations
442
Base Timer
442
Specification
442
Time Measurement Function
450
Waveform Generation Function
454
Specification
455
I/O Port Select Function
466
Interrupts
467
IC/OC Base Timer Interrupt
468
IC/OC Channel 0 Interrupt to IC/OC Channel 3 Interrupt
468
IC/OC Interrupt 0 and IC/OC Interrupt 1
468
Notes on Timer S
469
Register Access
469
Changing the G1IR Register
469
Changing Registers Icociic (I = 0, 1)
471
Output Waveform During the Base Timer Reset with the BTS Bit
471
OUTC1_0 Pin Output During the Base Timer Reset with the G1PO0 Register
471
Interrupt Request When Selecting Time Measurement Function
471
19. Task Monitor Timer
472
Introduction
472
Registers
473
Task Monitor Timer Register (TMOS)
473
Task Monitor Timer Count Start Flag (TMOSSR)
473
Task Monitor Timer Count Source Select Register (TMOSCS)
474
Task Monitor Timer Protect Register (TMOSPR)
474
Operation
475
Interrupt
476
Notes on Task Monitor Timer
477
Register Settings
477
Reading the Timer
477
20. Real-Time Clock
478
Introduction
478
Registers
480
Real-Time Clock Second Data Register (RTCSEC)
481
Real-Time Clock Minute Data Register (RTCMIN)
482
Real-Time Clock Hour Data Register (RTCHR)
483
Real-Time Clock Day Data Register (RTCWK)
484
Real-Time Clock Control Register 1 (RTCCR1)
485
Real-Time Clock Control Register 2 (RTCCR2)
487
Real-Time Clock Count Source Select Register (RTCCSR)
489
Real-Time Clock Second Compare Data Register (RTCCSEC)
490
Real-Time Clock Minute Compare Data Register (RTCCMIN)
491
Real-Time Clock Hour Compare Data Register (RTCCHR)
492
Operations
493
Basic Operation
493
Compare Mode
496
Interrupts
502
Notes on Real-Time Clock
503
Starting and Stopping the Count
503
Register Settings (Time Data, Etc.)
503
Register Settings (Compare Data)
503
Time Reading Procedure in Real-Time Clock Mode
504
Serial Interface Uarti (I = 0 to 4)
505
Introduction
505
Registers
508
UART Clock Select Register (UCLKSEL0)
510
Peripheral Clock Select Register (PCLKR)
510
Uarti Transmit/Receive Mode Register (Uimr) (I = 0 to 4)
511
Uarti Bit Rate Register (Uibrg) (I = 0 to 4)
512
Uarti Transmit Buffer Register (Uitb) (I = 0 to 4)
512
Uarti Transmit/Receive Control Register 0 (Uic0) (I = 0 to 4)
513

Renesas M16C Series User Manual (846 pages)

Brand: Renesas | Category: Computer Hardware | Size: 10 MB

Table of Contents
8
Quick Reference
27
Overview
34
Features
34
Applications
34
Specifications
35
Product List
37
Block Diagram
39
Pin Assignments
40
Pin Functions
44
Central Processing Unit (CPU)
47
Data Registers (R0, R1, R2, and R3)
48
Address Registers (A0 and A1)
48
Frame Base Register (FB)
48
Interrupt Table Register (INTB)
48
Program Counter (PC)
48
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
48
Static Base Register (SB)
48
Flag Register (FLG)
48
Carry Flag (C Flag)
48
Debug Flag (D Flag)
48
Interrupt Enable Flag (I Flag)
49
Stack Pointer Select Flag (U Flag)
49
Processor Interrupt Priority Level (IPL)
49
Reserved Areas
49
Address Space
50
Memory Map
51
Accessible Area in each Mode
52
Special Function Registers (Sfrs)
53
Sfrs
53
Notes on Sfrs
71
Register Settings
71
Protection
73
Introduction
73
Register
73
Protect Register (PRCR)
73
Notes on Protection
75
Resets
76
Introduction
76
Registers
78
Processor Mode Register 0 (PM0)
79
Reset Source Determine Register (RSTFR)
80
Optional Function Select Area
81
Optional Function Select Address 1 (OFS1)
81
Operations
83
Status after Reset
83
Hardware Reset
86
Power-On Reset Function
87
Voltage Monitor 0 Reset
88
Voltage Monitor 1 Reset
88
Voltage Monitor 2 Reset
88
Oscillator Stop Detect Reset
89
Watchdog Timer Reset
89
Software Reset
89
Cold/Warm Start Discrimination
90
Notes on Resets
91
Power Supply Rising Gradient
91
Power-On Reset
91
OSDR Bit (Oscillation Stop Detect Reset Detect Flag)
92
Voltage Detector
93
Introduction
93
Registers
95
Voltage Detector 2 Flag Register (VCR1)
96
Voltage Detector Operation Enable Register (VCR2)
97
Voltage Monitor Function Select Register (VWCE)
98
Voltage Detector 1 Level Select Register (VD1LS)
99
Voltage Monitor 0 Control Register (VW0C)
100
Voltage Monitor 1 Control Register (VW1C)
101
Voltage Monitor 2 Control Register (VW2C)
103
Optional Function Select Area
105
Optional Function Select Address 1 (OFS1)
105
Operations
106
Digital Filter
106
Voltage Detector 0
107
Voltage Detector 1
109
Voltage Detector 2
112
Interrupts
115
Clock Generator
116
Introduction
116
Registers
118
Processor Mode Register 0 (PM0)
119
System Clock Control Register 0 (CM0)
120
System Clock Control Register 1 (CM1)
122
Oscillation Stop Detection Register (CM2)
124
Peripheral Clock Select Register (PCLKR)
126
Peripheral Clock Stop Register 1 (PCLKSTP1)
126
PLL Control Register 0 (PLC0)
128
Processor Mode Register 2 (PM2)
129
Clocks Generated by Clock Generators
130
Main Clock
130
PLL Clock
131
125 Khz On-Chip Oscillator Clock (Foco-S)
131
Sub Clock (Fc)
132
CPU Clock and Peripheral Function Clocks
133
CPU Clock and BCLK
133
Peripheral Function Clocks (F1, Foco-S, Fc32, Fc, Main Clock)
133
Clock Output Function
135
System Clock Protection Function
135
Oscillator Stop/Restart Detect Function
136
Operation When CM27 Bit Is 0 (Oscillator Stop Detect Reset)
136
Operation When CM27 Bit Is 1 (Oscillator Stop/Restart Detect Interrupt)
137
Using the Oscillator Stop/Restart Detect Function
138
Interrupt
138
Notes on Clock Generator
139
Oscillator Using a Crystal or a Ceramic Resonator
139
Noise Countermeasure
140
CPU Clock
141
Oscillator Stop/Restart Detect Function
141
PLL Frequency Synthesizer
142
Power Control
143
Introduction
143
Registers
143
Flash Memory Control Register 0 (FMR0)
144
Flash Memory Control Register 2 (FMR2)
145
Clock
147
Normal Operating Mode
147
CPU Clock
149
Clock Mode Transition Procedure
151
Wait Mode
154
Stop Mode
156
Power Control in Flash Memory
158
Stopping Flash Memory
158
Reading Flash Memory
159
Low Current Consumption Read Mode
160
Reducing Power Consumption
161
Ports
161
A/D Converter
161
D/A Converter
161
Stopping Peripheral Functions
161
Switching the Oscillation-Driving Capacity
161
Notes on Power Control
162
CPU Clock
162
Wait Mode
162
Stop Mode
162
Low Current Consumption Read Mode
163
Slow Read Mode
163
10. Processor Mode
164
Introduction
164
Registers
165
Processor Mode Register 0 (PM0)
165
Processor Mode Register 1 (PM1)
166
Program 2 Area Control Register (PRG2C)
168
Operations
169
Processor Mode Settings
169
11. Bus
171
Introduction
171
Registers
171
Chip Select Control Register (CSR)
172
Chip Select Expansion Control Register (CSE)
173
Operations
174
Common Specifications between the Internal Bus and External Bus
174
Internal Bus
175
External Bus
176
External Bus Mode
176
External Bus Control
177
Notes on Bus
186
Reading Data Flash
186
External Bus
186
External Access Immediately after Writing to the Sfrs
186
Hold
186
12. Memory Space Expansion Function
187
Introduction
187
Registers
187
Data Bank Register (DBR)
188
Operations
189
1-MB Mode
189
4-MB Mode
191
13. Programmable I/O Ports
198
Introduction
198
I/O Ports and Pins
199
Registers
211
Pull-Up Control Register 0 (PUR0)
212
Pull-Up Control Register 1 (PUR1)
213
Pull-Up Control Register 2 (PUR2)
214
Port Control Register (PCR)
215
Port Pi Register (Pi) (I = 0 to 10)
216
Port Pi Direction Register (Pdi) (I = 0 to 10)
217
NMI/SD Digital Filter Register (NMIDF)
218
Peripheral Function I/O
219
Peripheral Function I/O and Port Direction Bits
219
Priority Level of Peripheral Function I/O
219
NMI/SD Digital Filter
220
CNVSS Pin
220
Unassigned Pin Handling
221
Notes on Programmable I/O Ports
223
Influence of SD
223
Influence of SI/O3 and SI/O4
223
Interrupts
224
Introduction
224
Registers
225
Processor Mode Register 2 (PM2)
227
Interrupt Control Register 1
228
(INT7IC, INT6IC, INT3IC, S4IC/INT5IC, S3IC/INT4IC, INT0IC to INT2IC)
229
Interrupt Source Select Register 3 (IFSR3A)
230
Interrupt Source Select Register 2 (IFSR2A)
231
Interrupt Source Select Register (IFSR)
232
Address Match Interrupt Enable Register (AIER)
233
Address Match Interrupt Enable Register 2 (AIER2)
233
Address Match Interrupt Register I (Rmadi) (I = 0 to 3)
234
Port Control Register (PCR)
235
NMI/SD Digital Filter Register (NMIDF)
236
Types of Interrupts
237
Software Interrupts
238
Undefined Instruction Interrupt
238
Overflow Interrupt
238
BRK Interrupt
238
INT Instruction Interrupt
238
Hardware Interrupts
239
Special Interrupts
239
Peripheral Function Interrupts
239
Interrupts and Interrupt Vectors
240
Fixed Vector Tables
240
Relocatable Vector Tables
241
Interrupt Control
243
Maskable Interrupt Control
243
Interrupt Sequence
244
Interrupt Response Time
245
Variation of IPL When Interrupt Request Is Accepted
245
Saving Registers
246
Returning from an Interrupt Routine
247
Interrupt Priority
247
Interrupt Priority Level Select Circuit
247
Multiple Interrupts
249
INT Interrupt
249
NMI Interrupt
250
14.10 Key Input Interrupt
250
14.11 Address Match Interrupt
251
14.12 Non-Maskable Interrupt Source Discrimination
252
14.13 Notes on Interrupts
253
14.13.1 Reading Address 00000H
253
14.13.2 SP Setting
253
14.13.3 NMI Interrupt
253
14.13.4 Changing an Interrupt Source
254
14.13.5 Rewriting the Interrupt Control Register
255
14.13.6 Instruction to Rewrite the Interrupt Control Register
255
14.13.7 INT Interrupt
256
15. Watchdog Timer
257
Introduction
257
Registers
258
Voltage Monitor 2 Control Register (VW2C)
258
Count Source Protection Mode Register (CSPR)
259
Watchdog Timer Refresh Register (WDTR)
260
Watchdog Timer Start Register (WDTS)
260
Watchdog Timer Control Register (WDC)
261
Optional Function Select Area
262
Optional Function Select Address 1 (OFS1)
262
Operations
263
Count Source Protection Mode Disabled
263
Count Source Protection Mode Enabled
264
Interrupts
265
Notes on the Watchdog Timer
266
16. Dmac
267
Introduction
267
Registers
269
Dmai Source Pointer (Sari) (I = 0 to 3)
270
Dmai Destination Pointer (Dari) (I = 0 to 3)
270
Dmai Transfer Counter (Tcri) (I = 0 to 3)
271
Dmai Control Register (Dmicon) (I = 0 to 3)
272
Dmai Source Select Register (Dmisl) (I = 0 to 3)
273
Operations
276
DMA Enabled
276
DMA Request
276
Transfer Cycles
277
DMAC Transfer Cycles
279
Single Transfer Mode
280
Repeat Transfer Mode
281
Channel Priority and DMA Transfer Timing
282
Interrupts
283
Notes on DMAC
284
Write to the DMAE Bit in the Dmicon Register (I = 0 to 3)
284
Changing the DMA Request Source
284
17. Timer a
285
Introduction
285
Registers
288
Peripheral Clock Select Register (PCLKR)
289
Clock Prescaler Reset Flag (CPSRF)
289
Peripheral Clock Stop Register 1 (PCLKSTP1)
290
Timer a Count Source Select Register I (Tacsi) (I = 0 to 2)
291
16-Bit Pulse Width Modulation Mode Function Select Register (PWMFS)
292
Timer a Waveform Output Function Select Register (TAPOFS)
293
Timer a Output Waveform Change Enable Register (TAOW)
294
Timer Ai Register (Tai) (I = 0 to 4)
295
Timer Ai-1 Register (Tai1) (I = 1, 2, 4)
296
Count Start Flag (TABSR)
296
One-Shot Start Flag (ONSF)
297
Trigger Select Register (TRGSR)
298
Increment/Decrement Flag (UDF)
299
Timer Ai Mode Register (Taimr) (I = 0 to 4)
300
Operations
301
Common Operations
301
Timer Mode
303
Event Counter Mode (When Not Using Two-Phase Pulse Signal Processing)
307
Event Counter Mode (When Processing Two-Phase Pulse Signal)
311
One-Shot Timer Mode
316
Pulse Width Modulation (PWM) Mode
320
Programmable Output Mode (Timers A1, A2, and A4)
325
Interrupts
329
Notes on Timer a
330
Common Notes on Multiple Modes
330
Timer a (Timer Mode)
331
Timer a (Event Counter Mode)
331
Timer a (One-Shot Timer Mode)
331
Timer a (Pulse Width Modulation Mode)
332
Timer a (Programmable Output Mode)
333
18. Timer B
334
Introduction
334
Registers
337
Peripheral Clock Select Register (PCLKR)
338
Clock Prescaler Reset Flag (CPSRF)
338
Peripheral Clock Stop Register 1 (PCLKSTP1)
339
Timer Bi Register (Tbi) (I = 0 to 5)
340
Timer Bi-1 Register (Tbi1) (I = 0 to 5)
341
Pulse Period/Pulse Width Measurement Mode Function Select Register I (Ppwfsi) (I = 1, 2)
342
Timer B Count Source Select Register I (Tbcsi) (I = 0 to 3)
343
Count Start Flag (TABSR) Timer B3/B4/B5 Count Start Flag (TBSR)
344
Timer Bi Mode Register (Tbimr) (I = 0 to 5)
345
Operations
346
Common Operations
346
Timer Mode
348
Event Counter Mode
350
Pulse Period/Pulse Width Measurement Modes
353
Interrupts
358
Notes on Timer B
359
Common Notes on Multiple Modes
359
Timer B (Timer Mode)
359
Timer B (Event Counter Mode)
359
Timer B (Pulse Period/Pulse Width Measurement Modes)
360
19. Three-Phase Motor Control Timer Function
361
Introduction
361
Registers
365
Timer B2 Register (TB2)
366
Timer Ai, Ai-1 Register (Tai, Tai1) (I = 1, 2, 4)
366
Three-Phase PWM Control Register 0 (INVC0)
367
Three-Phase PWM Control Register 1 (INVC1)
369
Three-Phase Output Buffer Register I (Idbi) (I = 0, 1)
371
Dead Time Timer (DTT)
371
Timer B2 Interrupt Generation Frequency Set Counter (ICTB2)
372
Timer B2 Special Mode Register (TB2SC)
373
Position-Data-Retain Function Control Register (PDRF)
374
Port Function Control Register (PFCR)
375
Three-Phase Protect Control Register (TPRC)
375
Operations
376
Common Operations in Multiple Modes
376
Triangular Wave Modulation Three-Phase Mode 0
382
Triangular Wave Modulation Three-Phase Mode 1
387
Sawtooth Wave Modulation Mode
394
Interrupts
399
Timer B2 Interrupt
399
Timer A1, A2, and A4 Interrupts
399
Notes on Three-Phase Motor Control Timer Function
400
Timer a and Timer B
400
Influence of SD
400
20. Real-Time Clock
401
Introduction
401
Registers
403
Real-Time Clock Second Data Register (RTCSEC)
404
Real-Time Clock Minute Data Register (RTCMIN)
405

Renesas M16C Series User Manual (367 pages)

16-BIT SINGLE-CHIP MICROCOMPUTER

Brand: Renesas | Category: Computer Hardware | Size: 3 MB

Renesas M16C Series Reference Book (32 pages)

16-BIT SINGLE-CHIP MICROCOMPUTER

Brand: Renesas | Category: Computer Hardware | Size: 0 MB

Table of Contents
4
Usage Precaution
6
Precautions for Power Control
6
Precautions for Protect
7
Precautions for Interrupts
8
Reading Address 0000016
8
Setting the SP
8
Changing the Interrupt Generate Factor
9
Rewrite the Interrupt Control Register
10
Watchdog Timer Interrupt
11
Precautions for DMAC
12
Write to DMAE Bit in Dmicon Register
12
Precautions for Timers
13
Timer a
13
Timer a (Timer Mode)
13
Timer a (Event Counter Mode)
14
Timer a (One-Shot Timer Mode)
15
Timer a (Pulse Width Modulation Mode)
16
Timer B
17
Timer B (Timer Mode)
17
Timer B (Event Counter Mode)
18
Timer B (Pulse Period/Pulse Width Measurement Mode)
19
Precautions for Serial I/O (Clock-Synchronous Serial I/O)
20
Transmission/Reception
20
Transmission
21
Reception
22
Precautions for Serial I/O (UART Mode)
23
Special Mode 2
23
Special Mode 4 (SIM Mode)
23
Precautions for A-D Converter
24
Precautions for Programmable I/O Ports
26

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