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Flash Self-Programming Library
Note
4.6 Dual CPU operation
Figure 4-6
4.7 Option Bytes
R01US0046ED Rev. 1.01
User Manual
Regardless which method is used, interrupt service routines have to be executed
from and therefore copied to RAM. For details how to copy the routines to RAM,
please refer to chapter 4.3 "Code execution in RAM".
Further information about interrupt handling from RAM can be found in the device
user manual and in the CPU architecture description (see "V850E2R-V3
Architecture").
In case of a dual CPU device the usage of the FSL is not limited to one CPU. The
Flash memory can be controlled by each CPU.
Data access bus
(high speed)
Service functions
RAM
Dual CPU operation causes some smaller restrictions. The service functions are
always located in RAM area of CPU1. Therefore the function response time will
increase in case of control by CPU2.
A second restriction is access control in general. To provide a fail safe
mechanism, only access by one CPU at a time is allowed. Simultaneous access
by the other CPU is prohibited. Access rights are controlled automatically by the
library.
The Extra Area contains user specific configuration data called Option Bytes.
These configuration settings are adjustable via Self-Programming. The size of the
Option Bytes is 4Byte. For details about possible configuration settings please
refer to the device user manual.
Flash Memory
CPU1
Dual CPU operation
FSL Usage
CPU2
RAM
CPU-CPU memory access
bus
(low speed)
24
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