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M30245 Group
4.4 Connectable Memories
4.4.1 Operation Frequency and Access Time
Connectable memories depend upon the BCLK frequency f(BCLK). The frequency of f(BCLK) is equal to
that of the BCLK, and is contingent on the oscillator's frequency and on the settings in the system clock
select bits (bit 6 of address 0006
The following are the conditional equations for the connections. Meet these conditions minimally. Fig-
ures 4.4.1 and 4.4.2 show the relation between the frequency of BCLK and memory.
(1) Read cycle time (tCR)/write cycle time (tCW)
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Read cycle time (tCR) and write cycle time (tCW) must satisfy the following conditional expressions:
• With the Wait option cleared
tCR < 10
(When CSxW = 1 read: one cycle of BCLK write: two cycles of BCLK)
• With the Wait option selected
tCR < (m+1) × 10
(When CSxW = 0 and the number of the expansion waits is selected by the CSExW bit)
(m denotes the number of Wait states: m = "1" when 1 wait selected, "m = 2" when 2 waits selected,
and "m = 3" when 3 waits selected)
(2) Address access time [ta(A)]
Address access time [ta(A)] must satisfy the following conditional expressions:
(a) Vcc = 3.0 to 3.6 V
• With the Wait option cleared
ta(A) < 10
• With the Wait option selected
ta(A) < (m+1) × 10
(m = "1" when 1 wait selected, "m = 2" when 2 waits selected, and "m = 3" when 3 waits selected)
*80(ns) = td(BCLK – AD) + tsu(DB – RD) – th(BCLK – RD)
(3) Chip select access time [ta(S)]
Chip select access time [ta(S)] must satisfy the following conditional expressions:
(a) Vcc = 3.0 to 3.6 V
• With the Wait option cleared
ta(S) < 10
• With the Wait option selected
ta(S) < (m+1) × 10
(m = "1" when 1 wait selected, "m = 2" when 2 waits selected, and "m = 3" when 3 waits selected)
*80(ns) = td(BCLK – CS) + tsu(DB – RD) – th(BCLK – RD)
Rev.2.00 Oct 16, 2006
REJ09B0340-0200
, and bits 6 and 7 of address 0007
16
/f(BCLK) and tCW < 2 × 10
9
/f(BCLK) and tCW < (m+1) × 10
9
9
/f(BCLK) – 80(ns)*
9
/f(BCLK) – 80(ns)*
= (address output delay time) + (data input setup time) – (RD signal output hold time)
9
/f(BCLK) – 80(ns)*
9
/f(BCLK) – 80(ns)*
= (chip select output delay time) + (data input setup time) – (RD signal output hold time)
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9
/f(BCLK)
9
/f(BCLK)
4. External Buses
).
16
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