Pwm (D/A) Data Registers A And B (Dadra And Dadrb) - Renesas H8S/2158 User Manual

Section 11 14-Bit PWM Timer (PWMX)
11.3.2

PWM (D/A) Data Registers A and B (DADRA and DADRB)

DADRA corresponds to PWM (D/A) channel A, and DADRB to PWM (D/A) channel B. The
DADR registers cannot be accessed in 8-bit units. The DADR registers should always be accessed
in 16-bit units. For details, see section 11.4, Bus Master Interface.
DADRA
Bit Bit Name Initial Value
15 DA13 1
14 DA12 1
13 DA11 1
12 DA10 1
11 DA9 1
10 DA8 1
9 DA7 1
8 DA6 1
7 DA5 1
6 DA4 1
5 DA3 1
4 DA2 1
3 DA1 1
2 DA0 1
1 CFS 1
0 — 1
Rev. 3.00 Jan 25, 2006 page 276 of 872
REJ09B0286-0300
R/W Description
R/W D/A Data 13 to 0
R/W
These bits set a digital value to be converted to an
R/W
analog value.
R/W
In each base cycle, the DACNT value is continually
R/W
compared with the DADR value to determine the duty
R/W
cycle of the output waveform, and to decide whether to
R/W
output a fine-adjustment pulse equal in width to the
R/W
resolution. To enable this operation, this register must
R/W
be set within a range that depends on the CFS bit. If the
R/W
DADR value is outside this range, the PWM output is
R/W
held constant.
R/W
R/W
A channel can be operated with 12-bit precision by
R/W
keeping the two lowest data bits (DA1 and DA0) cleared
to 0. The two lowest data bits correspond to the two
highest bits in DACNT.
R/W Carrier Frequency Select
0: Base cycle = resolution (T) × 64
DADR range = H'0401 to H'FFFD
1: Base cycle = resolution (T) × 256
DADR range = H'0103 to H'FFFF
R Reserved
This bit is always read as 1 and cannot be modified.