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Section 9 14-Bit PWM Timer (PWMX)
9.3.2
PWMX (D/A) Data Registers A and B (DADRA and DADRB)
DADRA corresponds to PWMX (D/A) channel A, and DADRB to PWMX (D/A) channel B. As
DACNT is 16 bits, data transfer between the CPU is performed through the temporary register
(TEMP). For details, see section 9.4, Bus Master Interface.
• DADRA
Bit
Bit Name
15
DA13
14
DA12
13
DA11
12
DA10
11
DA9
10
DA8
9
DA7
8
DA6
7
DA5
6
DA4
5
DA3
4
DA2
3
DA1
2
DA0
1
CFS
0
Rev. 1.00 Apr. 28, 2008 Page 222 of 994
REJ09B0452-0100
Initial
Value
R/W
Description
1
R/W
D/A Data 13 to 0
1
R/W
These bits set a digital value to be converted to an
analog value.
1
R/W
In each base cycle, the DACNT value is continually
1
R/W
compared with the DADR value to determine the duty
1
R/W
cycle of the output waveform, and to decide whether to
output a fine-adjustment pulse equal in width to the
1
R/W
resolution. To enable this operation, this register must
1
R/W
be set within a range that depends on the CFS bit. If
1
R/W
the DADR value is outside this range, the PWM output
is held constant.
1
R/W
A channel can be operated with 12-bit precision by
1
R/W
fixing DA0 and DA1 to 0. The two data bits are not
1
R/W
compared with DACNT12 and DACNT13 of DACNT.
1
R/W
1
R/W
1
R/W
1
R/W
Carrier Frequency Select
0: Base cycle = resolution (T) × 64
1: Base cycle = resolution (T) × 256
1
R
Reserved
Always read as 1 and cannot be modified.
The range of DA13 to DA0: H'0100 to H'3FFF
The range of DA13 to DA0: H'0040 to H'3FFF
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