Examples Of Register Setting - Renesas R8C Series User Manual

R8C/1A Group, R8C/1B Group
16.3.7

Examples of Register Setting

Figures 16.46 to 16.49 show Examples of Register Setting When Using I
Figure 16.46 Example of Register Setting in Master Transmit Mode (I
Rev.1.30 Dec 08, 2006
REJ09B0252-0130
Start
Initial setting
Read BBSY bit in ICCR2 register
No
BBSY = 0 ?
Yes
TRS bit ← 1
ICCR1 register
MST bit ← 1
SCP bit ← 0
ICCR2 register
BBSY bit ← 1
Write transmit data to ICDRT register
Read TEND bit in ICSR register
No
TEND = 1 ?
Yes
Read ACKBR bit in ICIER register
No
ACKBR = 0 ?
Yes
No
Transmit
mode ?
Yes
Write transmit data to ICDRT register
Read TDRE bit in ICSR register
No
TDRE = 1 ?
Yes
No
Last byte ?
Yes
Write transmit data to ICDRT register
Read TEND bit in ICSR register
No
TEND = 1 ?
Yes
TEND bit ← 0
ICSR register
STOP bit ← 0
ICSR register
SCP bit ← 0
ICCR2 register
BBSY bit ← 0
Read STOP bit in ICSR register
No
STOP = 1 ?
Yes
TRS bit ← 0
ICCR1 register
MST bit ← 0
TDRE bit ← 0
ICSR register
End
Page 227 of 315
16. Clock Synchronous Serial Interface
2
C bus interface.
• Set the STOP bit in the ICSR register to 0.
• Set the IICSEL bit in the PMR register to 1.
(1) Judge the state of the SCL and SDA lines.
(2) Set to master transmit mode.
(1)
(3) Generate the start condition.
(4) Set the transmit data of the 1st byte
(slave address + R/W).
(2)
(5) Wait for 1 byte to be transmitted.
(3)
(6) Judge the ACKBR bit from the specified slave device.
(7) Set the transmit data after 2nd byte (except the last byte).
(4)
(8) Wait until the ICRDT register is empty.
(9) Set the transmit data of the last byte.
(5)
(10) Wait for end of transmission of the last byte.
(11) Set the TEND bit to 0.
(12) Set the STOP bit to 0.
(13) Generate the stop condition.
(6)
(14) Wait until the stop condition is generated.
(15) Set to slave receive mode
Set the TDRE bit to 0.
Master receive
mode
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
2
C bus Interface Mode)