Csc0 And Csc1 Register Setting Example (64 Mb Mode) - Renesas NU85E Preliminary User's Manual

Examples 1. The following figure shows an example of CSC0 and CSC1 register settings for 64 MB mode and
the memory map after the settings are made.
Figure 4-3. CSC0 and CSC1 Register Setting Example (64 MB Mode) (1/3)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSC0 1 1 1 1 1 1 1 1 1 1 1 1 0
Notes 1. Since the high priority signal from the bit 0 setting (VDCSZ0) corresponds to bank 0, the setting in
bank 0 becomes invalid.
2. Since the high priority signal from the bit 1 setting (VDCSZ0) corresponds to bank 1, the setting in
bank 1 becomes invalid.
3. Since the high priority signal from the bit 10 setting (VDCSZ2) corresponds to bank 2, the setting in
bank 2 becomes invalid.
4. Since the high priority signal from the bit 11 setting (VDCSZ2) corresponds to bank 3, the setting in
bank 3 becomes invalid.
5. Since the high priority signal from the bit 6 setting (VDCSZ1) corresponds to bank 4, the setting in
bank 4 becomes invalid.
6. Since the high priority signal from the bit 7 setting (VDCSZ1) corresponds to bank 5, the setting in
bank 5 becomes invalid.
CHAPTER 4 BCU
(a) CSC0 register settings
0 1 1
VDCSZ0 (when accessing bank 0)
VDCSZ0 (when accessing bank 1)
VDCSZ1 (when accessing bank 0 or 1)
VDCSZ1 (when accessing bank 2 or 3)
VDCSZ1 (when accessing bank 4)
VDCSZ1 (when accessing bank 5)
VDCSZ2 (when accessing bank 0)
VDCSZ2 (when accessing bank 1)
VDCSZ2 (when accessing bank 2)
VDCSZ2 (when accessing bank 3)
VDCSZ3
(when accessing bank 0, 1, 2, or 3)
VDCSZ3 (when accessing bank 4 or 5)
VDCSZ3 (when accessing bank 6)
VDCSZ3 (when accessing bank 7)
Preliminary User's Manual A14874EJ3V0UM
VDCSZn signals that become active
Note 1
Note 2
Notes 1, 2
Notes 3, 4
Notes 1, 2, 3, 4
Notes 5, 6
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