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Section 7 I/O Ports
Noise Canceler Decision Control Register (PnNCMC) (n = 6, C, and G)
7.1.7
NCMC controls whether 1 or 0 is expected for the input signal to port n pins in bit units.
Bit
Bit Name
7
Pn7NCMC
6
Pn6NCMC
5
Pn5NCMC
4
Pn4NCMC
3
Pn3NCMC
2
Pn2NCMC
1
Pn1NCMC
0
Pn0NCMC
Noise Cancel Cycle Setting Register (PnNCCS) (n = 6, C, and G)
7.1.8
NCCS controls the sampling cycles of the noise canceler.
Bit
Bit Name
7 to 3
2
PnNCCK2
1
PnNCCK1
0
PnNCCK0
Rev. 1.00 Apr. 28, 2008 Page 150 of 994
REJ09B0452-0100
Initial Value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Initial Value
R/W
Undefined
R/W
0
R/W
0
R/W
0
R/W
Description
1 expected: 1 is stored in the port data register
when 1 is input stably.
0 expected: 0 is stored in the port data register
when 0 is input stably.
Description
Reserved
The read value is undefined. The write value
should always be 0.
These bits set the sampling cycles of the noise
canceler.
When φ is 10 MHz
0.80 µs
000:
12.8 µs
001:
010:
3.3 ms
011:
6.6 ms
100:
13.1 ms
101:
26.2 ms
110:
52.4 ms
111:
104.9 ms
φ/2
φ/32
φ/8192
φ/16384
φ/32768
φ/65536
φ/131072
φ/262144
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