Data Read Dummy Cycle Setting Register (Drdmcr) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
17.4.20

Data Read Dummy Cycle Setting Register (DRDMCR)

DRDMCR is a 32-bit register that sets the size and number of dummy cycles to be inserted in external address space read
mode.
The settings of this register are enabled when the DME bit in the data read enable setting register (DRENR) is 1.
The settings of this register should be changed when the TEND flag in CMNSR is 1; otherwise, the operation cannot be
guaranteed.
Bit: 31
-
Initial value: 0
R/W: R
Bit: 15
-
Initial value: 0
R/W: R
Bit Bit Name
31 to 18 ―
17, 16 DMDB
[1:0]
15 to 3 ―
2 to 0 DMCYC
[2:0]
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
30 29 28 27 26
- - - - -
0 0 0 0 0
R R R R R
14 13 12 11 10
- - - - -
0 0 0 0 0
R R R R R
Initial
Value R/W
All 0 R
00 R/W
All 0 R
000 R/W
25 24 23 22 21
- - - - -
0 0 0 0 0
R R R R R
9 8 7 6 5
- - - - -
0 0 0 0 0
R R R R R
Description
Reserved
These bits are always read as 0. The write value should always be 0.
Dummy Cycle Bit Size
Sets the dummy cycle size in bit units.
The setting of these bits is combined with the setting of the IO0FV, IO2FV,
and IO3FV bits in the common control register (CMNCR) to determine the
state of the unused pins during the dummy cycles.
The state of the used pins is Hi-Z.
00: 1 bit
01: 2 bits
10: 4 bits
11: Setting prohibited
Reserved
These bits are always read as 0. The write value should always be 0.
Number of Dummy Cycles
Sets the number of dummy cycles to be inserted when the DME bit in the
data read enable setting register (DRENR) is 1.
000: 1 cycle
001: 2 cycles
010: 3 cycles
011: 4 cycles
100: 5 cycles
101: 6 cycles
110: 7 cycles
111: 8 cycles
17. SPI Multi I/O Bus Controller
20 19 18 17 16
- - - DMDB[1:0]
0 0 0 0 0
R R R R/W R/W
4 3 2 1 0
- - DMCYC[2:0]
0 0 0 0 0
R R R/W R/W R/W
17-26