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Section 9 16-Bit Timer
Bit 3—Reserved: This bit cannot be modified and is always read as 1.
Bits 2 to 0—I/O Control A2 to A0 (IOA2 to IOA0): These bits select the GRA function.
Bit 2
Bit 1
IOA2
IOA1
0
0
1
1
0
1
Notes: 1. After a reset, the output conforms to the TOLR setting until the first compare match.
2. Channel 2 output cannot be toggled by compare match. This setting selects 1 output
instead.
9.2.11
Timer Output Level Setting Register C (TOLR)
TOLR is an 8-bit write-only register that selects the timer output level for channels 0 to 2.
Bit
Initial value
Read/Write
Reserved bits
A TOLR setting can only be made when the corresponding bit in TSTR is 0.
TOLR is a write-only register; if read, a value of 1 will be returned.
TOLR is initialized to H'C0 by a reset and in standby mode.
Rev. 4.00 Jan 26, 2006 page 356 of 938
REJ09B0276-0400
Bit 0
IOA0
Function
0
GRA is an output
compare register
1
0
1
0
GRA is an input
compare register
1
0
1
7
6
5
TOB2
1
1
0
W
No output at compare match
0 output at GRA compare match *
1 output at GRA compare match *
Output toggles at GRA compare match
(1 output in channel 2) *
GRA captures rising edge of input
GRA captures falling edge of input
GRA captures both edges of input
4
3
2
TOA2
TOB1
TOA1
0
0
0
W
W
W
Output level setting A2 to A0, B2 to B0
These bits set the levels of the timer outputs
(TIOCA
to TIOCA
2
0
(Initial value)
1
1
1
*
2
1
0
TOB0
TOA0
0
0
W
W
, and TIOCB
to TIOCB
2
)
0
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