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Section 8 I/O Ports
Noise Cancel Cycle Setting Register (PnNCCS) (n = 4, 6, C, and G)
8.1.8
NCCS controls the sampling cycles of the noise canceler.
Bit
Bit Name
7 to 3
2
PnNCCK2
1
PnNCCK1
0
PnNCCK0
t
Pin
Latch
input
Sampling
clock
Rev. 1.00 May 09, 2008 Page 162 of 954
REJ09B0462-0100
Initial Value
R/W
Undefined
R/W
0
R/W
0
R/W
0
R/W
φ/2, φ/32, φ/8192, φ/16384, φ/32768,
φ/65536, φ/131072, φ/262144
Sampling clock selection
Latch
Latch
t
Figure 8.1 Noise Cancel Circuit
Description
Reserved
The read value is undefined. The write value
should always be 0.
These bits set the sampling cycles of the noise
canceler.
When φ is 10 MHz
0.80 µs
000:
12.8 µs
001:
010:
3.3 ms
011:
6.6 ms
100:
13.1 ms
101:
26.2 ms
110:
52.4 ms
111:
104.9 ms
Latch
φ/2
φ/32
φ/8192
φ/16384
φ/32768
φ/65536
φ/131072
φ/262144
Port data
register
Interrupt input
Keyboard input
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