Table of Contents
Advertisement
13. Dot Matrix LCD Controller (H8/3857 Group)
13.2.5
Frame Frequency Setting Register (LR3)
Bit
7
⎯
⎯
Initial value
⎯
Read/Write
LR3 is an 8-bit write-only register that sets the frame frequency.
Upon reset, LR3 is initialized to H'00.
Bits 7 and 6—Reserved Bits: Bits 7 and 6 are reserved; they should always be cleared to 0.
Bits 5 to 0—Frame Frequency Setting (FS5 to FS0): Bits 5 to 0 control the subclock division
ratio and set the LCD frame frequency. The relationship between the LCD frame frequency f F
(Hz), the subclock frequency f W (Hz), the division ratio r, and the LCD duty 1/N is as follows:
Set a division ratio suitable for the characteristics of the LCD panel used. The correspondence
between register settings and division ratios is shown in table 13.3.
Rev.3.00 Jul. 19, 2007 page 336 of 532
REJ09B0397-0300
6
5
⎯
FS5
FS4
⎯
0
⎯
W
W
f
=
F
4
3
2
FS3
FS2
0
0
0
W
W
f
W
r
×
N
1
0
FS1
FS0
0
0
W
W
Advertisement
Table of Contents
