Extended Control Register (Exr); Vector Base Register (Vbr); Short Address Base Register (Sbr) - Renesas H8SX/1500 Series Hardware Manual

Section 2 CPU
2.5.4

Extended Control Register (EXR)

EXR is an 8-bit register that contains the trace bit (T) and three interrupt mask bits (I2 to I0).
Operations can be performed on the EXR bits by the LDC, STC, ANDC, ORC, and XORC
instructions.
For details, see the hardware manual for the corresponding product.
Bit Bit Name
7 T

6 to 3
2 I2
1 I1
0 I0
2.5.5

Vector Base Register (VBR)

VBR is a 32-bit register in which the upper 20 bits are valid. The lower 12 bits of this register are
read as 0s. This register is a base address of the vector area for exception handlings other than a
reset and a CPU address error (extended memory indirect is also out of the target). The initial
value is H'00000000. The VBR contents are changed with the LDC and STC instructions.
2.5.6

Short Address Base Register (SBR)

SBR is a 32-bit register in which the upper 24 bits are valid. The lower eight bits are read as 0s. In
8-bit absolute address addressing mode (@aa:8), this register is used as the upper address. The
initial value is H'FFFFFF00. The SBR contents are changed with the LDC and STC instructions.
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Initial
Value R/W Description
0 R/W Trace Bit
When this bit is set to 1, a trace exception is generated
each time an instruction is executed. When this bit is
cleared to 0, instructions are executed in sequence.
All 1 R/W Reserved
These bits are always read as 1.
1 R/W Interrupt Mask Bits
1 R/W These bits designate the interrupt mask level (0 to 7).
1 R/W