Dtc Enable Registers (Dtcer); Dtc Vector Register (Dtvecr) - Renesas H8S Series Hardware Manual

CRB is a 16-bit register that designates the number of times data is to be transferred by the DTC in block transfer mode. It
functions as a 16-bit transfer counter (1 to 65,536) that is decremented by 1 every time data is transferred, and transfer
ends when the count reaches H'0000.
8.2.7

DTC Enable Registers (DTCER)

Bit : 7
DTCE7
Initial value : 0
R/W : R/W
The DTC enable registers comprise six 8-bit readable/writable registers, DTCERA to DTCERF, with bits corresponding to
the interrupt sources that can activate the DTC. These bits enable or disable DTC service for the corresponding interrupt
sources.
The DTC enable registers are initialized to H'00 by a reset and in hardware standby mode.
Bit n—DTC Activation Enable (DTCEn)
Bit n
DTCEn
0
1
A DTCE bit can be set for each interrupt source that can activate the DTC. The correspondence between interrupt sources
and DTCE bits is shown in table 8-4, together with the vector number generated for each interrupt controller.
For DTCE bit setting, read/write operations must be performed using bit-manipulation instructions such as BSET and
BCLR. For the initial setting only, however, when multiple activation sources are set at one time, it is possible to disable
interrupts and write after executing a dummy read on the relevant register.
8.2.8

DTC Vector Register (DTVECR)

Bit : 7
SWDTE DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0
Initial value : 0
R/W : R/(W)*
Note: * A value of 1 can always be written to the SWDTE bit, but 0 can only be written after 1 is read.
DTVECR is an 8-bit readable/writable register that enables or disables DTC activation by software, and sets a vector
number for the software activation interrupt.
DTVECR is initialized to H'00 by a reset and in hardware standby mode.
6 5
DTCE6 DTCE5
0 0
R/W R/W
Description
DTC activation by this interrupt is disabled
[Clearing conditions]
•
When the DISEL bit is 1 and the data transfer has ended
•
When the specified number of transfers have ended
DTC activation by this interrupt is enabled
[Holding condition]
When the DISEL bit is 0 and the specified number of transfers have not ended
6 5
0 0
R/W R/W
4 3
DTCE4 DTCE3 DTCE2
0 0
R/W R/W R/W
4 3
0 0
R/W R/W R/W
2 1 0
DTCE1 DTCE0
0 0 0
R/W R/W
2 1 0
0 0 0
R/W R/W
Rev.6.00 Oct.28.2004 page 247 of 1016
(Initial value)
(n = 7 to 0)
REJ09B0138-0600H