Dtc Vector Register (Dtvecr) - Renesas H8S/2158 User Manual

7.2.8

DTC Vector Register (DTVECR)

DTVECR enables or disables DTC activation by software, and sets a vector number for the
software activation interrupt.
Bit Bit Name Initial Value
7 SWDTE 0
6 DTVEC6 0
5 DTVEC5 0
4 DTVEC4 0
3 DTVEC3 0
2 DTVEC2 0
1 DTVEC1 0
0 DTVEC0 0
R/W Description
R/W DTC Software Activation Enable
Setting this bit to 1 activates DTC. Only 1 can be written
to this bit.
[Clearing conditions]
1. When the DISEL bit is 0 and the specified number of
transfers have not ended
2. When 0 is written to the DISEL bit after a software-
activated data transfer end interrupt (SWDTEND)
request has been sent to the CPU.
This bit will not be cleared when the DISEL bit is 1 and
data transfer has ended or when the specified number
of transfers have ended.
R/W DTC Software Activation Vectors 6 to 0
R/W
These bits specify a vector number for DTC software
R/W
activation.
R/W
The vector address is expressed as H'0400 + (vector
R/W
number × 2). For example, when DTVEC6 to DTVEC0 =
R/W
H'10, the vector address is H'0420. When the SWDTE
R/W
bit is 0, these bits can be written to.
Section 7 Data Transfer Controller (DTC)
Rev. 3.00 Jan 25, 2006 page 151 of 872
REJ09B0286-0300