Section 6 Bus Controller (Bsc); Features - Renesas H8S/2437 Hardware Manual

This LSI has an on-chip bus controller (BSC) that manages the bus width and the number of
access states of the external address space.
6.1

Features

• Extended modes
Two modes for external extension
Normal extended mode: Normal extension (when the ADMXE bit in BCR is 0)
Address-data multiplex extended mode: Multiplex extension (when the ADMXE bit in BCR is
1)
• Extended area division
The external address space is divided into a basic area, and three 64-kbyte areas
The basic area and area 1 are for common settings. Area 2 and 3 bus specifications can be set
independently
Areas 1, 2, and 3 enable chip-select (CS1 to CS3) output
A maximum of 16 addresses can be output
• Area select signal, address strobe/hold signal polarity control
• It is possible to reverse the output polarity of CS1 to CS3 and AS/AH by the PNCCS bit in
BCRAn or the PNCASH bit in BCR
Normal Extension:
Address output pins (A15 to A0) and data input/output pins (D15 to D0) are separate
• Usable areas
Basic area and areas 1, 2, and 3 are all usable
• Normal extended bus interface
Selection between 2-state access area and 3-state access area is possible
Program wait state insert is possible
• Idle cycle insertion
Idle cycle insert is possible during the external write cycle, directly after external read cycle.
BSCS200A_000020020300

Section 6 Bus Controller (BSC)

Rev. 1.00, 09/03, page 91 of 704