Section 6 Bus Controller (Bsc); Features; Figure 6.1 Block Diagram Of Bus Controller - Renesas H8SX/1520 Series Hardware Manual

This LSI has an on-chip bus controller (BSC) that has a bus arbitration function and controls the
operation of the internal bus masters; CPU and DMAC.
6.1

Features

• Write data buffer function
Write access to an on-chip peripheral module and access to the on-chip memory can be
performed in parallel.
• Bus arbitration function
Includes a bus arbiter that arbitrates bus mastership between the CPU and DMAC.
Bus mastership can be shared between the CPU and DMAC when a conflict occurs.
• Multi-clock function
On-chip peripheral functions can be synchronized with the on-chip peripheral module clock
(Pφ).
A block diagram of the bus controller is shown in figure 6.1.
Downloaded from Elcodis.com electronic components distributor

Section 6 Bus Controller (BSC)

Internal bus
control signals
CPU bus mastership acknowledge signal
DMAC bus mastership acknowledge signal
CPU bus mastership request signal
DMAC bus mastership request signal
Internal data bus
[Legend]
BCR2: Bus control register 2

Figure 6.1 Block Diagram of Bus Controller

Section 6 Bus Controller (BSC)
Internal bus
control unit
Internal
bus
arbiter
Control register
BCR2
Rev. 3.00 Mar. 14, 2006 Page 125 of 804
REJ09B0104-0300