Internal Interrupts; Figure 5.2 Block Diagram Of Interrupts Irq15 To Irq0 - Renesas H8S/2368 Series Hardware Manual

When IRQ7 to IRQ0 interrupt requests occur at low level of IRQn, the corresponding IRQ should
be held low until an interrupt handling starts. Then the corresponding IRQ should be set to high in
the interrupt handling routine and clear the IRQnF bit (n = 0 to 7) in ISR to 0. Interrupts may not
be executed when the corresponding IRQ is set to high before the interrupt handling starts.
Detection of IRQ7 to IRQ0 interrupts does not depend on whether the relevant pin has been set for
input or output. However, when a pin is used as an external interrupt input pin, do not clear the
corresponding DDR to 0 and use the pin as an I/O pin for another function.
A block diagram of interrupts IRQ7 to IRQ0 is shown in figure 5.2.
IRQnSCB, IRQnSCA
input
Note: n = 7 to 0

Figure 5.2 Block Diagram of Interrupts IRQ15 to IRQ0

5.4.2

Internal Interrupts

The sources for internal interrupts from on-chip peripheral modules have the following features:
• For each on-chip peripheral module there are flags that indicate the interrupt request status,
and enable bits that select enabling or disabling of these interrupts. They can be controlled
independently. When the enable bit is set to 1, an interrupt request is issued to the interrupt
controller.
• The interrupt priority level can be set by means of IPR.
• The DMAC* and DTC can be activated by a TPU, SCI, or other interrupt request.
• When the DMAC* or DTC is activated by an interrupt request, it is not affected by the
interrupt control mode or CPU interrupt mask bit.
Note: * Not supported by the H8S/2366.
Edge/
level detection
circuit
Clear signal
IRQnE
IRQnF
S Q
R
Rev. 2.00, 05/03, page 91 of 820
IRQn interrupt
request