Internal Interrupts; Interrupt Exception Handling Vector Table; Figure 5.2 Block Diagram Of Interrupts Irq7 To Irq0 - Renesas H8S/2437 Hardware Manual

Detection of IRQ7 to IRQ0 interrupts does not depend on whether the relevant pin has been set for
input or output. However, when a pin is used as an external interrupt input pin, do not clear the
corresponding DDR to 0 and use the pin as an I/O pin for another function.
A block diagram of interrupts IRQ7 to IRQ0 is shown in figure 5.2.
IRQnSCA, IRQnSCB
input
Note: n = 15 to 0

Figure 5.2 Block Diagram of Interrupts IRQ7 to IRQ0

5.4.2

Internal Interrupts

The sources for internal interrupts from on-chip peripheral modules have the following features:
• For each on-chip peripheral module there are flags that indicate the interrupt request status,
and enable bits that select enabling or disabling of these interrupts. They can be controlled
independently. When the enable bit is set to 1, an interrupt request is sent to the interrupt
controller.
• The interrupt priority level can be set by means of IPR.
5.5

Interrupt Exception Handling Vector Table

Table 5.2 shows interrupt exception handling sources, vector addresses, and interrupt priorities.
For default priorities, the lower the vector number, the higher the priority. When interrupt control
mode 2 is set, priorities among modules can be changed by means of the IPR. Modules set at the
same priority will conform to their default priorities. Priorities within a module are fixed.
Rev. 1.00, 09/03, page 76 of 704
Edge/
level detection
circuit
Clear signal
IRQnE
IRQnF
S Q
R
IRQn interrupt
request